Physical Design Jobs
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Physical Design Engineer Jobs
Browse the latest physical design engineer jobs at leading semiconductor companies worldwide. Physical design (PD) engineers translate circuit schematics into manufacturable chip layouts, responsible for floorplanning, placement, routing, timing closure, and power optimization at advanced process nodes.
This page aggregates open physical design jobs across top semiconductor companies, including roles in:
- Chip floorplanning and power domain planning engineer jobs
- Place and route (PnR) engineer roles
- Static timing analysis (STA) and timing closure engineer jobs
- Power integrity and IR drop analysis roles
- Signal integrity and crosstalk mitigation engineering
- Physical verification and DRC/LVS signoff engineer jobs
Physical design engineers work at companies including NVIDIA, AMD, Apple, Qualcomm, Broadcom, Intel, Marvell, and leading chip design startups. These roles are critical to translating RTL designs into tape-ready chip layouts at advanced nodes including 3nm, 5nm, and 7nm.
Create a free account to receive alerts when new physical design jobs are posted and stay current on the latest openings in semiconductor layout and implementation engineering.
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SoC Engineering Intern
Synopsys
Internship
On-site
Yerevan, AM
November 5, 2026
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ASIC Physical Design Staff Engineer
Synopsys
Full-time
On-site
Hyderabad, Telangana, India
November 5, 2026
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Senior Engineer - Physical Design
Synopsys
Full-time
On-site
Hyderabad, Telangana, India
November 5, 2026
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Senior Staff FAE, RTL to GDS Implementation
Synopsys
Full-time
On-site
Bengaluru, Karnataka, India
November 5, 2026
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Layout Design Staff Engineer
Synopsys
Full-time
On-site
Bengaluru, Karnataka, India
November 5, 2026
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Principal D2D SerDes & Analog Layout Design Engineer
Microsoft
Full-time
Remote friendly (Mountain View, California, United States)
Worldwide
$142,800 - $274,800 USD yearly
November 5, 2026
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Physical Digital Design Engineer (CN Campus)
Monolithic Power Systems
Full-time
On-site
Chengdu, Sichuan, China
November 5, 2026
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Intern - Design Engineering
Cadence Design Systems
Internship
On-site
Shanghai, China
November 5, 2026
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MTS Design Architect - Custom Layout, HBM
Micron Technology
Full-time
On-site
Richardson, Texas, United States
November 5, 2026
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Layout/Mask Designer
Micron Technology
Full-time
On-site
Boise, Idaho, United States
November 5, 2026
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Sign upAlready have an account? Click hereBBanking Engineer
Farrell, Collins and Mohr
Full-time
Scranton, PA
United States
$50,000 - $70,000
1 week ago