ASIC Physical Design Staff Engineer

Job Title

ASIC Physical Design Staff Engineer

Role Summary

Senior static timing analysis (STA) engineer focused on timing closure for high-performance memory IP (DDR, LPDDR, HBM) and SoC designs. You will own STA from constraint development through signoff, drive automation, and collaborate with RTL, physical design, and verification teams across global sites.

Experience Level

Senior - 5 to 9 years of relevant experience in static timing analysis and timing closure.

Responsibilities

Key day-to-day responsibilities for this role:

• Close timing across multiple corners and operating modes for memory IP and SoC designs.
• Own static timing analysis workflow from constraint creation to final signoff using PrimeTime, PTECO, and DMSA.
• Debug and resolve complex timing violations, including asynchronous domain crossings and multi-corner convergence issues.
• Implement ECOs to fix functional and timing problems while minimizing collateral impact.
• Develop and maintain automation (Python, Tcl, Perl, shell) for STA, report generation, and ECO implementation.
• Collaborate with physical design, RTL, and verification teams across global sites to meet timing, power, and area targets.
• Identify bottlenecks in the RTL2GDS flow and propose tooling or methodology improvements.

Requirements

Required technical skills and experience; separate list for desirable qualifications.

• 5 to 9 years of hands-on experience in static timing analysis and timing closure at chip or IP level.
• Deep working knowledge of Synopsys PrimeTime, PTECO, and distributed multi-scenario analysis tools (DMSA).
• Proven experience closing timing on high-performance designs, ideally memory IP (DDR, LPDDR, HBM).
• Strong scripting skills in Python, Tcl, Perl, or shell to automate STA workflows and reports.
• Solid understanding of timing constraints, asynchronous timing analysis, and multi-corner/multi-mode closure strategies.
• Ability to analyze timing reports quickly and prioritize actionable issues over noise.
• Strong communication skills for translating timing findings into actionable guidance for RTL and physical design teams.

Nice-to-have:

• Experience with physical design flows and RTL2GDS implementation.
• Experience mentoring engineers on timing closure best practices and constraint development.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Science, or a related technical field.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.