Layout Design Staff Engineer
SynopsysJob Title
Layout Design Staff Engineer
Role Summary
Lead development of physical layout for DDR, HBM, and UCIe PHY IP on 7nm and below process nodes (FinFET and GAA). Deliver floorplans and layouts that meet timing, power, area, and manufacturability targets while coordinating across analog design, verification, and foundry teams.
Experience Level
Senior - typically requires 5+ years of hands-on layout design experience in analog, mixed-signal, or PHY IP development.
Responsibilities
Accountable for end-to-end layout delivery and technical leadership.
- Lead layout development for DDR, HBM, and UCIe PHY IP on advanced nodes (7nm and below).
- Own floorplanning, matching, ESD design, latch-up mitigation, and DFM compliance for analog/mixed-signal blocks.
- Perform and drive PERC and EMIR analysis, layout reviews, quality checks, and release processes.
- Mentor and provide hands-on technical guidance to junior layout engineers.
- Collaborate with analog designers, verification engineers, and foundry partners to meet schedules and customer requirements.
- Estimate effort, plan schedules, and execute multi-site, cross-functional layout projects.
- Support bond-pad layout, IO frame design, pitch requirements, and LEF generation for customer-facing deliverables.
Requirements
Essential technical skills and proven delivery in deep-submicron layout.
- 5+ years of hands-on layout design experience in analog, mixed-signal, or PHY IP development.
- Demonstrated experience with FinFET and GAA process technologies at 7nm and below.
- Deep understanding of deep-submicron effects and ability to make tradeoffs under constraints.
- Expertise in layout matching techniques, ESD design, latch-up mitigation, DFM practices, and LEF generation.
- Experience performing PERC and EMIR analysis and interpreting current-density reports for layout fixes.
- Proven ability to lead layout projects from floorplan through release while meeting quality and schedule commitments.
- Experience with bond-pad layout, IO frame design, and pitch requirements for high-speed interfaces.
- Ability to communicate effectively with analog designers, verification teams, and foundry contacts in cross-functional settings.
Education Requirements
BTech or MTech in Electronics Engineering, VLSI, or a related field.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
