Principal D2D SerDes & Analog Layout Design Engineer

Job Title

Principal D2D SerDes & Analog Layout Design Engineer

Role Summary

Technical lead for matching‑critical analog layout and die‑to‑die (D2D) SerDes physical implementation within Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE). Responsible for establishing layout strategy, driving complex subsystem execution across internal and external teams, and delivering production‑ready IP from feasibility through tapeout and silicon learning.

Works with circuit, PHY, package, signal‑integrity, CAD, and SoC integration teams to define integration constraints and ensure production signoff for advanced‑node analog and D2D IP.

Experience Level

Level: Senior (Principal). Typical expectation: experienced candidate with roughly 8+ years of analog/mixed‑signal layout and D2D/SerDes implementation experience; alternative degree‑based experience combinations apply (see Education Requirements).

Responsibilities

Primary responsibilities include strategic layout definition, technical execution, quality control, and cross‑team coordination for D2D SerDes and analog subsystems.

• Own physical implementation strategy and execution for D2D SerDes and analog/mixed‑signal subsystems from feasibility to tapeout and silicon learning.
• Define top‑level floorplans, partitioning, die‑edge constraints, bump/micro‑bump alignment, ESD, power delivery, routing, and package‑aware tradeoffs.
• Establish matching, isolation, and parasitic‑control methodology (symmetry, common‑centroid, interdigitation, dummy structures, shielding, guard rings, return‑path planning).
• Lead multi‑block execution across internal teams and external partners: plan implementations, set quality expectations, run reviews, and drive milestone and signoff closure.
• Translate extracted‑layout limits into clear architectural recommendations affecting circuit, PHY, package, SI, CAD, and SoC integration.
• Resolve high‑impact layout risks for transmit/receive paths, clocking, bias, equalization, PLL/DLL and related analog front‑end circuitry.
• Drive physical verification and production signoff strategy (DRC, LVS, ERC, extraction, EMIR, reliability, waiver judgment, hierarchical closure).
• Define layout quality criteria, review checklists, release requirements, and produce signoff deliverables (GDS/OASIS, LEF abstracts, interface documentation).
• Develop automation, templates, and methodology using SKILL, TCL, Python and Cadence APR or equivalent flows to scale delivery and productivity.
• Mentor senior engineers, govern third‑party contributors, and communicate technical strategy and risks to engineering and program leadership.

Requirements

Must‑have skills and conditions for consideration. Degree requirements are summarized separately under Education Requirements.

• Extensive analog and mixed‑signal transistor‑level layout experience with matching‑critical designs and complex subsystem integration in advanced processes.
• Experience with high‑speed SerDes or D2D interfaces and related analog front‑end circuitry (TX/RX, PLL/DLL, equalization, clocking, bias).
• Proven physical implementation through floorplanning, verification, signoff, tapeout, and integration; strong signoff knowledge (DRC/LVS/ERC, extraction‑aware layout, EMIR, reliability).
• Hands‑on experience with Cadence Virtuoso and Siemens/Mentor Calibre (or equivalent) for layout and physical verification.
• Experience defining physical implementation for advanced packaging and chiplet integration (die‑edge planning, bump interfaces, package escape, power and SI constraints).
• Strong automation and methodology development skills (SKILL, Python, TCL, Perl or similar); experience with Cadence APR flows is valuable.
• Practical experience with advanced nodes (FinFET/GAA, 5nm/3nm or beyond) and layout‑dependent effects mitigation.
• Demonstrated ability to lead cross‑organizational teams, govern external partners, and mentor senior engineers.
• Ability to meet Microsoft security screening and export control requirements and to provide citizenship or residency documentation as required for access to controlled information.

Education Requirements

Required: one of the following or equivalent experience - Doctorate (PhD) in Electrical Engineering, Computer Engineering, Computer Science, or a related field plus 3+ years relevant engineering experience; Master’s degree in EE/CE/CS or related plus 6+ years experience; Bachelor’s degree in EE/CE/CS or related plus 8+ years experience; or equivalent practical experience.

About the Company

Company: Microsoft

Headquarters: Redmond, Washington, United States

Microsoft is a global technology company that develops and sells software, services, devices, and solutions. Known for its Windows operating system, Office suite, and Azure cloud platform, Microsoft aims to empower individuals and organizations around the world to achieve more. The company fosters a culture of innovation and inclusion, focusing on delivering trusted experiences to customers and partners globally.