Physical Digital Design Engineer (CN Campus)

Job Title

Physical Digital Design Engineer (CN Campus)

Role Summary

Responsible for backend physical implementation of digital and mixed-signal ASICs. Work within the digital chip team to develop physical design flows, perform implementation tasks, and deliver tapeout-ready layouts.

Experience Level

Mid-level engineer. Specific years of experience were not provided.

Responsibilities

Primary tasks include physical implementation, verification, and collaboration with circuit designers.

• Develop physical design and verify digital and mixed-signal chips.
• Floorplanning, power and clock distribution, place-and-route, and static timing analysis.
• Drive LVS/DRC closure and layout verification convergence.
• Collaborate with digital and analog designers to physically implement custom analog blocks, interfaces, and IPs.

Requirements

Key skills and capabilities required or preferred for the role.

• Must-have: Good English reading, writing, and oral communication; ability to work independently and follow established processes to deliver high-quality results.
• Must-have: Familiarity with scripting and automation: Perl, TCL, Unix shell, Python.
• Nice-to-have: Experience with ASIC digital backend or related backend implementation experience.

Education Requirements

Master's degree in Microelectronics, Electronic Engineering, or a closely related field.

About the Company

Company: Monolithic Power Systems

Headquarters: San Jose, California, USA

Monolithic Power Systems, Inc. (MPS) is a leading provider of energy-efficient power solutions for various applications, including industrial, telecom, automotive, and consumer sectors. Known for their cutting-edge integrated power semiconductors, MPS emphasizes innovation, sustainability, and creativity, making them one of the fastest-growing companies in the semiconductor industry.