Senior Staff FAE, RTL to GDS Implementation

Job Title

Senior Staff FAE, RTL to GDS Implementation

Role Summary

Customer-facing application engineering role supporting RTL-to-GDS implementation at advanced process nodes. You will deploy and validate backend flows, debug physical-implementation issues, and translate customer problems into actionable R&D requirements.

Work with Synopsys product and field teams to ensure customers achieve timing, power, and area targets and to drive tool and methodology improvements.

Experience Level

Senior - 10+ years of ASIC design or application engineering experience.

Responsibilities

Key responsibilities include direct customer support, flow validation, benchmarking, and translating findings into product improvements.

• Deploy Fusion Compiler and ICC2 on customer designs at advanced nodes (5nm, 3nm, and below) and resolve complex PPA challenges.
• Develop, debug, and optimize RTL-to-GDS implementation flows; identify and remove timing, area, or power bottlenecks.
• Run competitive benchmarks and document quality-of-results (QoR) to support evaluations and displacement efforts.
• Translate customer issues into clear requirements for R&D and validate delivered enhancements on customer designs.
• Lead customer migration to new tool versions by validating flows, finding regressions, and ensuring production-quality results.
• Serve as the technical bridge between customers and R&D; represent customer needs and product capabilities accurately.
• Develop reusable solutions, scripts, and methodologies that scale across customers and designs.

Requirements

Must-have technical skills and experience to perform the role; nice-to-have items are listed separately.

• Must-have: 10+ years of hands-on ASIC design or application engineering experience with deep expertise in physical implementation (placement, optimization, CTS, routing).
• Must-have: Expert-level experience with Synopsys backend tools, specifically Fusion Compiler and ICC2, including physical synthesis and timing-closure techniques.
• Must-have: Strong working knowledge of the RTL-to-GDS full flow and the ability to debug issues from synthesis through signoff.
• Must-have: Proven experience working directly with customers or cross-functional teams under tight schedules.
• Must-have: Deep understanding of advanced-node design challenges (5nm and below) and the methodologies to meet timing, power, and area targets at scale.
• Nice-to-have: Experience with static timing analysis tools such as PrimeTime and familiarity with front-end synthesis flows (Design Compiler or Fusion Compiler front end).

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field - or equivalent practical experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.