Skip to main content
Semiconductor Design Blog - Career Guides & Industry Insights

Semiconductor Design Career Resources

Guides, industry insights, and career advice for IC engineers, ASIC designers, and chip architects.

All "Job Role Variations 5G modem 5G modem design AI chip AI chip design AMD AMD jobs ARM server CPU jobs ASIC ASIC Design ASIC design ASIC design jobs ATPG Alphawave Semi Ampere Computing Analog Analog Design Analog Simulation Ansys RedHawk Apple jobs Apple silicon Arm Arm Cortex-M Austin semiconductor jobs Back-End Design Boston semiconductor jobs Broadcom Broadcom jobs CDC CPU Design CPU core design CPU design CTS CXL Cadence Cadence Allegro Cadence Conformal Cadence Genus Cadence Innovus Cadence JasperGold Cadence Quantus Cadence Spectre Cadence Tempus Cadence Virtuoso Cadence Voltus Cadence Xcelium Calibre jobs Career Chip Design Company-Specific Keywords DDR DFT DSP DV jobs Design Compiler jobs Director Distinguished Engineer ECO flows EDA EDA Tools Keywords Embedded Entry Level Ethernet ASIC design Exynos FPGA FPGA design FPGA jobs FPGA prototyping Floorplanning Fusion Compiler GPU GPU architecture GaN RF design Geographic/Location Keywords HBM HFSS jobs HSPICE Hiring IC Design Leadership IC Design Management IC design IC design engineer jobs IC design leadership ICC2 jobs IP design IR-drop Infineon Technologies Intel Intel jobs Internships IoT semiconductors JasperGold Job Role Variations LEC Lattice Semiconductor Low Power Low Power Design ML accelerator Marvell Marvell jobs MediaTek MediaTek jobs Microchip Technology Mixed-Signal ModelSim NVIDIA NVIDIA jobs NXP Semiconductors New Grad PCB design PDN design PDN signoff PLL design Parasitic Extraction PhD engineering Physical Design PnR Power Analysis Power Integrity PrimeTime jobs Principal Engineer Qorvo Qualcomm Qualcomm RF IC Qualcomm jobs Questa jobs RF IC design RF design RISC-V RTL RTL Design RTL Lint RTL design RTL lint RTL synthesis Raleigh semiconductor jobs Renesas jobs Research Triangle chip design SRAM engineer STA STA engineer STMicroelectronics Samsung Samsung jobs San Diego chip design jobs San Jose semiconductor jobs Santa Clara Seattle semiconductor jobs Senior IC Design Senior Level Seniority Level Keywords SerDes design jobs Siemens Calibre Siemens Questa Siemens Tessent Signoff Silicon Valley Silicon Valley chip design Skyworks SoC Architecture SoC Design SoC design SoC integration SpyGlass Staff Engineer Staff Level Supply Chain Synopsys Synopsys DCG Synopsys Formality Synopsys HAPS Synopsys ICC2 Synopsys Laker Synopsys PrimePower Synopsys PrimeTime Synopsys StarRC Synopsys VC Formal Synopsys VCS Synopsys ZeBu SystemVerilog TSMC jobs Testing Texas ASIC design Texas Instruments Texas Instruments jobs Timing Closure Timing Signoff UPF UVM UVM verification engineer VC Formal VC SpyGlass VLSI VLSI design VP design engineering VP engineering Verification Xcelium advanced-packaging analog IC design analog IC" analog design analog layout analog layout jobs analog simulation asic-design audio IC design automotive IC design jobs automotive-ic-design cache-coherent interconnect career chief design officer chip architect chip design chip design jobs chiplet-design clock domain crossing clock tree synthesis cloud ASIC design custom IC custom IC layout custom cell design custom layout data converters design enablement design for test design verification embedded IC design embedded processor emulation entry level entry level IC jobs entry-level executive IC jobs floorplanning formal verification formal-verification foundry functional coverage functional verification gpu-design graphics-chips hardware emulation hardware security hardware-security high-speed PHY high-speed design" interconnect interface IP interface-chip internships iso26262 junior junior IC engineer logic synthesis logical equivalence checking low-power-design memory controller memory design microarchitecture mid-career mid-level mid-level circuit jobs mid-level engineer mixed-signal mixed-signal IC design jobs mmWave mmwave-engineer netlist engineering networking ASIC new grad new grad DFT parasitic extraction pcie-design physical design physical design engineer physical verification physical verification engineer physical-design place and route place-and-route post-silicon validation power IC design power IC design jobs power analysis power delivery network power integrity power planning power signoff power-management pre-silicon validation pre-silicon verification principal engineer process design engineer processor design rf-ic-design rtl security-design-engineer semiconductor IP semiconductor design engineer semiconductor design jobs semiconductor leadership semiconductor verification senior DV senior FPGA engineer senior IC jobs senior digital senior emulation engineer signal integrity signal integrity engineer signal processing silicon bring-up staff engineer standard cells static timing analysis synthesis synthesis engineer synthesis-engineer tapeout test engineering timing closure verification verification engineer wafer-scale integration wireless IC design
Company-Specific Keywords Arm physical design

Arm Physical Design Engineer Jobs

Why physical design at Arm differs from ASIC PD, who hires for it, where, and what it pays.

Read more →
Company-Specific Keywords Intel jobs physical design

Intel Physical Design Engineer Jobs: Open Roles

What physical design work at Intel looks like when the fab is in-house, and where the openings are.

Read more →
Company-Specific Keywords physical design AMD

AMD Physical Design Engineer Jobs: Browse Open Positions

AMD physical design roles in San Jose, Austin, Hyderabad, and Markham: floorplan, place and route, and timing closure on TSMC chiplet designs.

Read more →
Company-Specific Keywords Broadcom physical design

Broadcom Physical Design Engineer Roles

What Broadcom physical design engineers actually do, which sites hire, and the tools you need to get in.

Read more →
EDA Tools Keywords Cadence Innovus physical design

Cadence Innovus Congestion Engineer Jobs: Find PnR Routing Roles

Cadence Innovus congestion engineer roles clear routing hotspots so ASIC blocks close on the tapeout schedule instead of slipping.

Read more →
EDA Tools Keywords Fusion Compiler physical design

Synopsys Fusion Compiler Engineer Jobs: One Flow, RTL to GDS

What Synopsys Fusion Compiler engineers actually do, which companies hire them, and what the role pays.

Read more →
Seniority Level Keywords physical design new grad

New Grad Physical Design Engineer Jobs: Start Your PnR Career

What new grad physical design engineer jobs expect, from Innovus and ICC2 fluency to the intern paths that feed them.

Read more →
Seniority Level Keywords physical design entry level IC jobs

"Entry Level Physical Design Engineer Jobs: Start Your PnR Career"

Entry level physical design roles for recent graduates ready to learn floorplanning, placement, routing, and timing closure in an industry setting.

Read more →
Seniority Level Keywords physical design PnR

Staff Physical Design Engineer Jobs: Find Senior PnR Roles

Staff physical design engineers define PnR methodology, lead tapeout programs, and own signoff criteria across complex SoC implementations.

Read more →
Seniority Level Keywords physical design mid-career

Mid-Level Physical Design Engineer Jobs: Browse PnR Roles

Mid-level physical design engineer jobs target PnR specialists with full tapeout experience who can independently drive block-level timing closure.

Read more →
Job Role Variations clock tree synthesis CTS physical design

Clock Tree Synthesis Engineer Jobs: Find CTS Roles

CTS engineers build the clock distribution networks that deliver synchronized edges to millions of flip-flops, and hiring is steady across advanced-node design teams.

Read more →