AMD Physical Design Engineer Jobs: Browse Open Positions
AMD's physical design teams take RTL for Zen CPUs, RDNA GPUs, and CDNA accelerators and turn it into tape-out-ready silicon on TSMC's leading nodes. The work lives at the back end of the flow: floorplanning, placement and routing, power grid design, clock tree synthesis, timing closure, and signoff.
These teams implement the compute dies, I/O dies, and GPU shader arrays behind EPYC, Ryzen, and Radeon. On a leading-edge node, the floorplan decisions you make early set the ceiling for what timing closure can recover later, so senior engineers spend nearly as much time planning as they do on the closing grind.
The roles reward fluency in Cadence Innovus or Synopsys ICC2, solid static timing analysis in PrimeTime or Tempus, and real experience closing timing on multi-die chiplet designs. If you already know AMD's chiplet architecture and the TSMC 5nm and 3nm design rules, your resume moves to the top of the pile.
Day to day, the job is IR drop analysis in Voltus, DRC and LVS sign-off in Calibre, and long timing-closure loops where a single ECO can ripple through the clock tree. AMD wraps the vendor flow in internal Python and Tcl automation, so scripting is not optional.
The chiplet strategy is what makes this different from PD work at a monolithic-die shop or an integrated device maker like Intel physical design, where the fab is in-house. You co-design with packaging engineers on die-to-die interconnect, bump placement, and thermal floorplanning, not just single-die implementation. Anyone who touches 3D V-Cache integration picks up advanced packaging co-design skills that are scarce across the AI chip market.
SemiDesignJobs lists AMD physical design openings from San Jose, CA; Austin, TX; Hyderabad, India; and Markham, Canada. Filter by product line (CPU, GPU, or FPGA), experience level, and location. For the wider AMD slate, browse AMD jobs for semiconductor designers.
Related listings sit under AMD RTL engineer positions and physical design engineer jobs in San Jose.
Pay for AMD physical design engineers in the US typically runs from about $130K to $180K base at the mid and senior levels, with staff and principal roles clearing more once stock and bonus land. The India and Canada sites price to local market. Save a search on semidesignjobs.com and you'll get an email when an AMD physical design role matches your filters.
FAQ
What EDA tools do AMD physical design engineers use
AMD physical design engineers mainly run Cadence Innovus for place and route, Synopsys PrimeTime for STA, Cadence Voltus for power analysis, and Siemens Calibre for DRC and LVS. Internal Python and Tcl automation wraps the vendor flow, so expect to read and extend scripts on day one.
How does AMD's chiplet strategy affect physical design engineer jobs
Chiplets push physical design engineers to work directly with packaging on die-to-die bump placement, thermal budgets, and power delivery across several dies at once. That cross-domain scope is rare, and it is exactly the experience AI-accelerator teams are paying up for right now.
What process nodes does AMD use for its chip designs
AMD builds on TSMC's leading nodes, N4 for current Zen 4 CPUs and RDNA 3 GPUs, with N3 coming for the next generation. Closing timing on these nodes gives you advanced-node experience that transfers to almost any high-performance design team.