Broadcom Physical Design Engineer Roles
Broadcom's networking silicon carries a large share of the world's internet traffic, and the teams that lay out chips like Tomahawk, Trident, and Jericho are hiring physical design engineers across several US and India design centers. These are back-end roles: you take gate-level netlists from the RTL teams and turn them into manufacturable layout.
The day-to-day is placement and routing, timing closure, power grid construction, and sign-off. Most groups run Cadence Innovus or Synopsys ICC2 for place and route, PrimeTime for static timing, Calibre for DRC and LVS, and Voltus for power integrity. Designs run into the tens of millions of gates, and the harder openings sit at 5nm and 3nm FinFET, where multi-patterning and local interconnect rules shape every floorplan decision. Broadcom also keeps plenty of work at mature nodes like 16nm and 28nm for cost-sensitive parts, so the role ladder spans new grad through principal.
Most of the hiring clusters in San Jose and Irvine, California, with additional teams in Fort Collins, Colorado, and Bangalore, India. Product-wise you'll land on networking ASICs, storage controllers such as MegaRAID and the HBA line, or broadband and wireless connectivity chips. If you've closed timing on a large SoC before, that experience transfers cleanly here.
Compensation tracks the rest of the Bay Area chip market. Senior physical design engineers at Broadcom generally see base pay around $150K to $210K, with total compensation reaching $220K to $320K at senior and staff levels once stock and bonus are counted. Our salary guide for semiconductor jobs breaks the numbers down by level and region.
SemiDesignJobs pulls Broadcom postings into one place so you can filter by discipline, location, and experience. Browse the current physical design engineer jobs, check related Broadcom VLSI roles, and save a search so you get an email the moment a new Broadcom physical design opening is posted.
FAQ
What tools do Broadcom physical design engineers use?
Mostly Cadence Innovus and Synopsys IC Compiler 2 for place and route, with PrimeTime for static timing analysis. Calibre for DRC and LVS and Voltus for power analysis show up on most job descriptions too.
What process nodes do Broadcom physical design teams target?
They span 28nm for cost-optimized parts up to 3nm FinFET for high-performance networking ASICs. Familiarity with sub-10nm issues like multi-patterning and local interconnect gives you a real edge in interviews.
What is the hiring process for Broadcom physical design engineer roles?
Usually a recruiter screen, a technical phone interview on physical design fundamentals, then a design loop with several engineers, on-site or virtual. Expect questions on timing closure, floorplanning, and power grid tradeoffs.