Mid-Level Physical Design Engineer Jobs: Browse PnR Roles
Physical design engineering hits a different gear around the three-to-seven-year mark. You're independently closing timing on blocks, making floorplan tradeoffs, and running ECO flows without someone reviewing every step. That's the experience level most employers are targeting for mid-level PD roles.
Companies at this stage expect at least one full tapeout cycle on your resume and proficiency in either Cadence Innovus or Synopsys ICC2. You should be comfortable driving timing closure through ECO iterations, resolving DRC and LVS violations in Siemens Calibre, and making power-grid decisions that hold up through signoff. Strong candidates also contribute methodology improvements, not just execute existing flows.
The broader physical design engineer jobs page covers PD roles at all levels. For engineers ready to take on full-chip or architecture-level block ownership, senior physical design engineer openings are the natural next step.
Qualcomm, Apple, Nvidia, and Marvell are among the largest employers for mid-level PD engineers. AI chip startups like Cerebras, Tenstorrent, and d-Matrix also hire at this level, often with more equity upside and the chance to own a larger portion of the physical implementation. Foundry-adjacent teams at TSMC's design enablement group offer deep exposure to advanced process nodes from a different angle.
Engineers who stand out tend to have node diversity: experience at both a mature node (28nm or 16nm) and an advanced node (7nm or 5nm). The physical design challenges shift significantly below 10nm with FinFET effects, multi-patterning constraints, and tighter power-density budgets. If you've only worked at one node, targeting a role at a different process is a practical way to broaden your profile.
Mid-level physical design engineers in Silicon Valley typically earn $160K to $220K in total compensation, with base salaries in the $150K to $200K range. Engineers with tapeout experience at 7nm or below command premiums. The salary guide has more granular data by location and company tier.
Browse physical design jobs on semidesignjobs.com to find mid-level openings that match your node experience and tool stack.
FAQ
What distinguishes a mid-level from a junior physical design engineer?
Mid-level physical design engineers independently own blocks through the full implementation cycle, from netlist handoff through timing signoff, without requiring constant guidance. They proactively identify issues, propose solutions, and contribute methodology improvements rather than waiting for direction.
How many tapeouts should I have for mid-level physical design engineer jobs?
At least one full tapeout cycle is the standard expectation. Engineers with two or more tapeouts across different technology nodes are particularly competitive. Quality matters more than quantity: a complex SoC tapeout at an advanced node (7nm or below) carries more weight than multiple simple designs at mature nodes.
What is the typical salary range for mid-level physical design engineer jobs?
Mid-level physical design engineers typically earn $150K to $200K base salary, with total compensation of $170K to $240K including equity and bonus at leading fabless companies. Compensation varies by company tier, node expertise, and location.