NVIDIA Interconnect Design Engineer Jobs

An NVIDIA AI system is only as fast as the links between its GPUs. NVLink, NVSwitch, and the NVLink-C2C die-to-die interconnect are what let a rack of Blackwell parts behave like one large accelerator, and the engineers who design those links sit where high-speed SerDes, physical design, and protocol work meet.

SemiDesignJobs tracks NVIDIA interconnect openings across the main design centers, including Santa Clara, Austin, and Yokneam in Israel. The common thread is high-speed signaling: PHY design, channel modeling, and multi-die packaging.

The work leans hard on SerDes above 50 Gbps. You model insertion loss and crosstalk across a package and board, run channel and signal-integrity simulation in tools like HSPICE or Cadence Spectre, and close timing on the PHY. Familiarity with PCIe Gen5/6, NVLink, or the UCIe die-to-die standard matters, and hands-on 3D-IC or chiplet integration experience is worth more every year as NVIDIA moves parts onto multi-die packages.

Blackwell and the NVLink Switch System are the current proving ground. A single NVLink domain now spans dozens of GPUs, so the interconnect is no longer a side feature of the chip. It is a large share of the design effort and one of the harder problems in the building.

If you want the full picture of NVIDIA and high-speed interface work, see NVIDIA ASIC design engineer jobs and the broader SerDes design engineer market.

Pay reflects how scarce senior SerDes and interconnect talent is. US roles at senior level commonly run $170K to $250K base, with total compensation well past that once stock is added; the salary guide breaks ranges down by level. Save a search on SemiDesignJobs and the alerts arrive when a new NVIDIA interconnect posting goes up.

FAQ

What skills are needed for NVIDIA interconnect design engineer jobs

These roles want high-speed SerDes design, signal-integrity analysis, and PHY architecture. Experience with NVLink, PCIe Gen5/6, or UCIe is highly valued, and strong channel-modeling skills in HSPICE or Cadence Spectre are close to required.

What interconnect technologies does NVIDIA develop

NVIDIA builds NVLink for GPU-to-GPU links, NVSwitch for multi-GPU fabric switches, NVLink-C2C for die-to-die connections in multi-chip modules, and standard PCIe interfaces. Together these carry the traffic inside NVIDIA's DGX and HGX systems in AI data centers.

Are NVIDIA interconnect design engineer roles remote-friendly

Most require on-site or hybrid presence given how hardware-intensive the work is, though some senior architecture and modeling roles allow more flexibility. SemiDesignJobs lists the work model on every posting so you can filter for it.