SerDes Design Engineer Jobs: Find High-Speed I/O Roles
SerDes circuits are the analog front-ends that move data at multi-Gbps rates between chips, modules, and across die-to-die interconnects. Every PCIe lane, Ethernet port, and proprietary chiplet bridge depends on a serializer-deserializer PHY to work. Data rates have climbed from 56 Gbps to 112 Gbps PAM-4 in production silicon, with 224 Gbps in active development, and the hiring pipeline for engineers who can design these circuits remains wide open.
The work is deeply analog and mixed-signal. Transmit-side engineers design driver equalization and pre-emphasis circuits. Receive-side engineers build CTLE and DFE equalizers to compensate for inter-symbol interference across lossy channels. Clock-data recovery PLL design is its own specialty, requiring tight jitter budgets that get harder to meet at every new data rate. Most SerDes PHY teams split into TX, RX, and CDR sub-block owners.
The primary design environment is Cadence Virtuoso for schematic and layout, Spectre for circuit simulation, and channel simulation tools like Ansys HFSS for link margin analysis. Closely related roles include PLL design engineer positions and signal integrity engineering.
Broadcom, Marvell, and Alphawave Semi hire the most dedicated SerDes designers. Nvidia, AMD, Intel, and Apple all have internal PHY teams too. AI chip startups building custom die-to-die links have become a newer source of openings. US base salaries for experienced SerDes designers run $150K to $190K, with total comp at staff level reaching $300K or more at the top-tier companies. The salary guide breaks this down by seniority and region.
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FAQ
What is a SerDes and why is it important in chip design
A serializer-deserializer converts parallel data to a high-speed serial stream for transmission and recovers parallel data from a received serial stream. SerDes are essential for all high-speed chip-to-chip communication, providing the bandwidth needed for PCIe, Ethernet, DDR, and proprietary interconnects at multi-Gbps rates.
What analog techniques are most important in SerDes design engineer jobs
CTLE and DFE design for ISI compensation, transmit pre-emphasis, and bang-bang or proportional-integral CDR PLL design are the core techniques. Adaptive algorithms for equalizer coefficient tuning become critical at 56 Gbps and above, where fixed equalization cannot track channel variation across process corners.
How are SerDes data rates evolving and what design challenges does this create
Rates have increased from 1 Gbps in early PCIe to 112 Gbps PAM-4 for modern Ethernet and die-to-die links, with 224 Gbps in development. Higher rates require more aggressive equalization, tighter PLL jitter specs, and careful analog layout to minimize noise coupling from digital supply domains.