Broadcom Ethernet ASIC Design Engineer Jobs
Almost every hyperscale data center on the planet moves packets through a Broadcom switch chip. The Tomahawk and Trident families set the line-rate ceiling for cloud networking, and the teams that build them keep hiring as 800G ramps in volume and 1.6T Ethernet moves from spec toward silicon.
Broadcom Ethernet ASIC design engineer jobs cover RTL design of switch fabric and packet-processing pipelines, MAC and PHY development, packet buffer and queue management, and high-speed SerDes integration on advanced TSMC nodes. You write SystemVerilog for blocks that carry petabits a day, close timing across wide datapaths, and hand lint- and CDC-clean RTL to synthesis and physical implementation. Knowing Ethernet from 100G through 800G, plus L2/L3 forwarding and the usual QoS mechanisms, is what separates a strong candidate from a general digital designer.
Broadcom runs these programs out of San Jose headquarters, Irvine, Andover in Massachusetts, Bangalore, and Singapore. Openings split by domain, front-end RTL, verification, physical design, and by seniority, so a single chip program often has a slot for a mid-career RTL engineer and a principal working switch architecture at the same time. Broadcom sits alongside the other companies hiring for semiconductor design tracked on the board.
AI traffic is the reason the hiring has not cooled off. Training clusters need east-west bandwidth that roughly doubles on a short cadence, which keeps the roadmap full and the design centers short-staffed.
Pay tracks the rest of the top ASIC tier. Senior engineers land six-figure base salaries, and total compensation at staff and principal levels commonly runs $250K to $400K once stock and bonus are counted. The Broadcom ladder goes senior, principal, distinguished, then fellow, so a deep specialist has room to climb without switching to management. The semiconductor salary guide breaks those ranges down by level.
Related Broadcom openings, including physical design roles and VLSI design jobs, sit next to these on the board. Save a Broadcom search on semidesignjobs.com and you will get an email when a new Ethernet ASIC role opens.
FAQ
What Ethernet products do Broadcom ASIC design engineers work on?
Broadcom's Ethernet teams design the Tomahawk (spine switching), Trident (leaf switching), and Jericho (routing) chip families used in hyperscale and enterprise data center networks. These chips run port rates from 25G to 800G and are the default choice in cloud networking.
What technical background is required for Broadcom Ethernet ASIC jobs?
You need solid RTL design in SystemVerilog, hands-on work with high-speed digital design (MAC, SerDes, or switch fabric), and familiarity with Ethernet standards. Knowledge of L2/L3 networking protocols, QoS, and physical-layer design is a real advantage.
What does career growth look like at Broadcom for ASIC design engineers?
Broadcom has a defined ladder from senior engineer up through principal, distinguished, and fellow. Most ASIC designers specialize deeply in one area, physical design, RTL, or verification, and can move into architect or lead roles running a major chip project.