NVIDIA ASIC Design Engineer Jobs
NVIDIA's ASIC teams sit behind the GPUs, NVLink switches, and DRIVE automotive silicon that anchor much of today's AI compute. The openings run across RTL design, physical implementation, and power optimization, and they show up at every level from new graduate to principal architect.
On SemiDesignJobs we pull the latest NVIDIA ASIC listings into one verified feed, so you are not stitching a search together across a dozen career pages. Filter by experience level, location, and sub-discipline, or jump straight to the full list of NVIDIA openings.
Most NVIDIA ASIC roles expect fluent SystemVerilog or VHDL, hands-on time with Synopsys Design Compiler or Cadence Innovus, and solid digital design fundamentals. Front-end engineers hand off lint- and timing-clean RTL to synthesis and physical design; implementation leads own floorplan, place and route, and signoff. The advanced work runs on 4nm and 3nm FinFET at TSMC, where compute density and the power budget are in constant tension.
The design work splits across GPU microarchitecture, networking through the Mellanox and NVLink teams, automotive on the DRIVE platform, and AI inference processors. The Blackwell generation pushed transistor counts into territory few other companies reach, so the RTL and implementation teams keep growing to match. Related front-end work shows up under NVIDIA RTL engineer positions.
Pay at NVIDIA usually combines a base salary, an annual bonus, and RSU grants that vest over four years, which pushes senior total comp well past base alone. Our salary guide lists ranges by role and level if you want to benchmark an offer.
If NVIDIA is not the only name on your list, AMD RTL engineer positions and the broader ASIC design engineer roles feed cover openings across the industry. If you have taped out at 5nm or below, these will read as familiar. Save a search on SemiDesignJobs and you will get an email the moment a new NVIDIA ASIC posting matches your filters.
FAQ
What qualifications do NVIDIA ASIC design engineer jobs require
Most roles ask for a BS or MS in Electrical or Computer Engineering, strong RTL coding in SystemVerilog or VHDL, and experience with production EDA tools. Prior work on advanced process nodes such as 5nm or 4nm is a clear advantage.
Where are NVIDIA ASIC design engineer positions located
The primary ASIC hubs are Santa Clara, CA, and Austin, TX, with additional teams in Bangalore and Tel Aviv. Some senior roles offer hybrid or remote flexibility. SemiDesignJobs lists the location on every posting.
How do I apply for NVIDIA ASIC design engineer jobs on SemiDesignJobs
Create a free account, search for NVIDIA ASIC design engineer jobs, and click Apply on any listing. You can also set up email alerts and hear the moment a new NVIDIA position goes up.