Custom Cell Design Engineer Jobs: Find Standard Cell Roles

Every digital ASIC synthesizes from a standard cell library, and custom cell design engineers are the people who build that library from scratch. The role sits at the intersection of analog circuit design and digital logic: you need enough transistor-level intuition to optimize a cell for speed, power, and area, and enough awareness of how synthesis tools consume the library to make characterization results meaningful.

The core workflow runs through Cadence Virtuoso. You draw the transistor-level schematic, create the full-custom layout, verify against DRC and LVS, then run SPICE characterization across thousands of input slew and output load corners to produce Liberty (.lib) timing and power models. Those models flow directly into Synopsys Design Compiler, Cadence Genus, and PrimeTime for synthesis and static timing analysis. If the characterization model is off, the chip's timing signoff is off. LEF abstracts for place-and-route and GDS for mask data round out the standard deliverable set.

At advanced FinFET nodes (5nm, 3nm), the constraints tighten significantly. Drive strength no longer scales continuously; it steps discretely by fin count. Minimum contacted poly pitch and fixed track height enforce strict layout templates, leaving little room for cell-level creativity but demanding precision on every design rule. Parasitic capacitance from fin and gate metal is more significant than in planar nodes, making accurate SPICE deck setup critical to Liberty accuracy.

Related disciplines include analog layout engineering and memory design engineering, both of which share full-custom design skills with standard cell work. Engineers who cross-train across all three are well-positioned for IP library roles.

Standard cell IP vendors like Arm and Synopsys IP Group hire for library development. Foundries including TSMC and Samsung develop process-native cell libraries internally. Large IDMs (Intel, Samsung LSI) maintain dedicated cell library teams, and some large fabless companies build internal libraries optimized for their leading-edge process engagements.

Compensation for custom cell design roles reflects the specialized transistor-level expertise involved. The semiconductor design salary guide has current ranges by role level, company type, and location.

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FAQ

What are standard cells and why are they fundamental to IC design?

Standard cells are pre-designed, pre-characterized logic building blocks: inverters, gates, flip-flops. Synthesis and place-and-route tools assemble them into digital circuits. Every digital ASIC is built from a standard cell library, so cell quality directly determines chip performance, power, and area.

What is Liberty characterization in custom cell design engineer jobs?

Liberty characterization runs SPICE simulations across thousands of input slew and output load conditions to generate timing and power (.lib) models for each cell. Synthesis and STA tools consume these models; inaccurate characterization means timing signoff doesn't reflect what the silicon will actually do.

How does custom cell design at FinFET nodes differ from planar CMOS?

FinFET standard cells use quantized fin widths, so drive strength scales in discrete steps by fin count rather than continuously. Minimum contacted poly pitch and fixed track height impose strict layout templates, and parasitics from fin and gate metal carry more weight than in planar nodes.