Memory Design Engineer Jobs: Find SRAM and Cache Roles
On-chip memory has evolved from a supporting element into a first-class design discipline. As AI accelerators pack hundreds of megabytes of on-chip SRAM and GPU cache hierarchies grow to serve thousands of compute lanes, companies are hiring engineers who specialize in memory structures, not just general ASIC designers who happen to work near an SRAM macro.
Memory design engineer jobs center on the custom design and characterization of on-chip memory structures: SRAM bitcells and arrays, register files, content-addressable memories (CAMs), and the memory compilers that package these into portable, process-tuned macros. When a design team calls a memory compiler with a configuration, they get back GDSII, LEF, Liberty timing models, and behavioral models, then move on. Building that compiler and keeping it accurate across process splits and voltage corners is the memory engineer's core deliverable.
At sub-5nm nodes the job grows harder. Bitcell read/write margins shrink, process variation sensitivity increases, and the team that once "just ported SRAM" is now running SPICE at minimum VDD across every PVT corner, adding assist circuits (negative bitline, VDD boosting, word-line overdrive), and negotiating bitcell specs directly with the fab.
Apple, Nvidia, AMD, and Qualcomm run dedicated memory design groups for CPU and GPU cache hierarchies. AI chip startups building inference accelerators hire memory engineers to design weight-storage SRAMs optimized for access bandwidth and power density. Embedded and automotive programs at Renesas, NXP, and Arm partners need engineers fluent in eNVM and security ROM design.
Compensation tracks ASIC seniority levels. Mid-level memory design engineers at established fabless companies typically earn $140K–$200K base; staff and principal roles at Apple or hyperscaler in-house teams run higher. The semiconductor salary guide has current data by geography and company type.
Analog IC design and physical design sit closest to memory design in the org chart: analog engineers handle bitcell schematics and SPICE, while physical design engineers assist with array floorplanning and timing closure of large macro boundaries.
Save a search on semidesignjobs.com with filters for SRAM, memory compiler, or cache architecture, and you'll get an email when a matching role opens.
FAQ
What types of memory are most common in memory design engineer jobs?
SRAM is the dominant type in digital IC design, used for caches, register files, and local data storage. Roles may also cover CAMs, ROM, and embedded non-volatile memory (eNVM) for security and configuration storage.
How does process node scaling affect memory design engineering?
At 5nm and 3nm, SRAM bitcell design faces shrinking read/write margins and higher process variation sensitivity. Memory engineers develop assist circuits including negative bitline, VDD boosting, and word-line overdrive to maintain reliable operation at minimum supply voltages.
What is a memory compiler and why is it important?
A memory compiler generates complete memory arrays from a parameterized configuration: schematics, layout (GDSII), timing models (Liberty), and LEF. Memory engineers build and maintain these compilers so chip teams can instantiate optimized memory macros without doing custom design work on each project.