Analog Layout Engineer Jobs: Find Custom IC Layout Roles
Analog layout is one of the most specialized disciplines in custom IC design. Where digital place-and-route runs largely automated, analog layout requires drawing every transistor geometry by hand, because device matching, noise shielding, and parasitic coupling are too sensitive for automation to handle reliably.
Work centers on implementing PLLs, ADCs, LDOs, bandgaps, and other precision analog circuits in Cadence Virtuoso. Beyond placing devices on silicon, the job involves managing device matching through careful common-centroid placement, isolating sensitive nodes with guard rings, and running RC extraction followed by post-layout simulation to verify that circuit performance meets spec. Siemens Calibre handles DRC and LVS verification.
At advanced nodes from 16nm FinFET down to 5nm, the rules add considerably. Fin quantization dictates discrete device widths, metal stack parasitics are more pronounced, and post-layout simulation is what determines whether a circuit actually hits spec in silicon, not the schematic. First-pass silicon success at these nodes is rare without a thorough post-layout sim loop.
Analog IC design engineers write the schematics that analog layout engineers implement physically; the two roles iterate closely throughout every design cycle. Knowing the schematic intent well enough to flag layout-driven degradation before simulation is what separates mid-level from senior analog layout engineers.
Engineers with deep Virtuoso expertise and tapeout experience at 7nm and below are scarce. Demand is strong at mixed-signal IP companies, mobile SoC teams at Qualcomm and MediaTek, and startups building power management or high-speed SerDes ICs. Apple Silicon and NVIDIA's analog teams also hire regularly.
Compensation for senior analog layout engineers with advanced process experience typically runs from $150K to $250K base, with total compensation at top-tier companies often higher. The specialized nature of the craft, combined with the years required to develop Virtuoso fluency across multiple PDKs, keeps supply tight relative to demand. For current ranges by seniority level, see the salary guide for semiconductor design jobs.
Browse ASIC design engineer jobs for roles where full-custom and digital layout skills overlap.
Set up a saved search on semidesignjobs.com; new analog layout openings appear as companies finalize headcount for upcoming tapeouts.
FAQ
What is the primary tool for analog layout engineer jobs?
Cadence Virtuoso Layout Suite is the dominant tool for analog and custom digital layout. Engineers use Virtuoso alongside Siemens Calibre for DRC/LVS verification and Cadence Quantus (QRC) or Synopsys StarRC for parasitic extraction feeding post-layout simulation.
How does analog layout at advanced nodes differ from mature nodes?
FinFET nodes introduce discrete fin quantization, mandating minimum device widths and imposing strict routing rules for sensitive analog nets. Parasitic capacitance from fins and metal stack interactions is more significant, making post-layout simulation essential and increasing the difficulty of achieving first-pass silicon performance.
Is Cadence Virtuoso experience required for analog layout engineer jobs?
Yes. Virtuoso is the industry standard for analog custom layout, and virtually all analog layout engineer job postings either require or strongly prefer Virtuoso experience. Familiarity with PDK design rules and process-specific layout guidelines for the target foundry is also expected.