Mid-Level Analog IC Design Engineer Jobs: Find Circuit Roles
Mid-level is where analog design starts to feel like your own. With 3 to 7 years of transistor-level work behind you, you take a block from spec to silicon-ready: a complete amplifier, a comparator, a bandgap, or a simpler filter stage, with a senior engineer steering architecture but not holding your hand through the simulation.
Companies hiring at this level expect Cadence Virtuoso fluency and SPICE simulation that goes past the basics: PSS and Pnoise for periodic and noise analysis, Monte Carlo for mismatch and yield. You should be able to drive post-layout simulation and clean up DRC and LVS with little support.
Working with custom layout engineers on the tricky analog cells is a standard part of the job. You write the layout guidelines, specify device matching and shielding for sensitive nodes, then run extraction and post-layout simulation to confirm the parasitics did not eat your phase margin.
The role sits above the general analog IC design roles and feeds toward senior and staff analog positions once you can own architecture decisions yourself.
Openings show up across mobile power management, data center and automotive analog, and the in-house teams at companies running their own PMICs and SerDes. The common thread at mid-level is a hiring manager who wants someone productive on day one but still coachable on architecture.
What trips up engineers at this stage is treating layout as someone else's problem. The strongest mid-level analog people own the block through silicon, staying on top of extraction results and reading the layout closely instead of waiting for the post-layout sim to fail. That habit is what gets you trusted with harder blocks and, in time, architecture work. Most teams also want you fluent on the verification side of analog: assertion-based checks on your testbenches and a clean handoff of behavioral models to the mixed-signal and SoC integration teams.
Before you negotiate, benchmark. The salary guide for semiconductor jobs shows the mid-level analog range by company type and region, which matters when offers swing widely between a startup and a large fabless shop.
Browse semidesignjobs.com for mid-level analog roles at companies with real analog mentorship, and save a search so a matching opening lands in your inbox.
FAQ
What simulations should a mid-level analog IC design engineer run independently
Run DC operating point, AC, transient, and process-corner simulations on your own. Be comfortable with PSS for PLL and switching-converter analysis, Pnoise for phase noise, and Monte Carlo for yield and mismatch. Setting up these testbenches from scratch, not just rerunning someone else's, is the expectation at mid-level.
How do mid-level analog engineers collaborate with layout engineers
You set the layout guidelines for your circuits: device placement for matching, shielding for sensitive nodes, acceptable parasitic ranges. You review the layout as it develops, run post-layout extraction and simulation to check that parasitics have not degraded performance, and iterate with the layout engineer until the block meets spec.
What process corner analysis is expected at the mid-level analog design level
Simulate across all process corners (TT, FF, SS, FS, SF) and the temperature range in the spec. Identify which corner limits performance, flag any specification violations, and propose circuit or topology changes to close the margin before layout starts. Catching a failing corner late is expensive, so this work happens early.