Place and Route Engineer Jobs: Browse PnR Openings

At 5nm and 3nm, place and route work is largely a congestion management problem. Gate count has grown faster than routing resources, so PnR engineers spend substantial time iterating placement, adjusting hierarchical floorplans, and feeding RTL feedback to design teams before a netlist even reaches the router.

The job covers the full physical implementation cycle: floorplan setup with pin placement and partition constraints, power grid construction from VDD/VSS stripes down to standard cell rails, global and detailed routing, DRC fixing, and ECO closure after STA sign-off. Multi-voltage domain handling and CTS awareness are assumed at mid-level and above. Some PnR roles at hyperscaler design teams carry DFM responsibilities for advanced nodes as well.

Cadence Innovus and Synopsys ICC2 handle the bulk of production PnR. Most teams standardize on one but expect working knowledge of the other. Full-chip integration engineers additionally use Synopsys PrimeTime for timing sign-off and Siemens Calibre for DRC.

Apple Silicon, Qualcomm, Nvidia, and AMD hire PnR engineers continuously for SoC and GPU tape-outs. AI chip startups scaling from first silicon to volume production add experienced PnR engineers as they move to 5nm and below. Broadcom and Marvell hire for networking and storage controllers, where power density and congestion management push beyond what standard flows handle out of the box. Hyperscaler in-house teams building custom accelerators are an increasingly active segment of the PnR job market.

Senior PnR engineers at fabless companies earn $170K–$240K total compensation. Staff and principal roles at Apple Silicon and Nvidia go higher for engineers with sub-7nm tapeout history. Entry and mid-level roles typically start in the $110K–$150K range. The semiconductor salary guide has a fuller breakdown by level and geography.

Floorplan engineering sits upstream from PnR in the physical design flow; timing closure engineering owns the downstream sign-off iteration. Both roles work alongside PnR through the full tapeout cycle.

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FAQ

What is the most widely used tool for place and route engineer jobs?

Cadence Innovus and Synopsys ICC2 are the two dominant tools. Most companies standardize on one or the other. Engineers fluent in both are more competitive, particularly when moving between fabless companies with different EDA agreements.

What process nodes are most common in place and route engineer jobs?

PnR roles exist across all nodes from 28nm down to 3nm. Advanced node roles at 7nm, 5nm, and 3nm are more demanding due to multi-patterning constraints and increased parasitic sensitivity, and they typically command higher compensation.

How does a PnR engineer collaborate with the STA team?

PnR engineers run timing analysis in parallel with routing iterations and share violation reports with dedicated STA engineers. When PnR cannot close timing through placement and routing changes alone, the STA team guides ECO strategies involving cell swaps, buffer insertion, and logic restructuring.