Physical Design Engineer Jobs: Find IC Back-End Roles

Physical design is the back-end of the ASIC flow: take a synthesized netlist, produce a manufacturable layout that hits timing, meets power and IR-drop budgets, and clears DRC and LVS. It's compute-heavy work with long tool turnarounds, which shapes both the workflow and the way teams are organized.

The day-to-day looks like floorplanning, power planning, placement and routing in Cadence Innovus or Synopsys ICC2, timing analysis in PrimeTime, and ECO implementation when timing closure gets stubborn. Signoff verification on DRC, LVS, and IR drop completes the loop before tapeout. Senior physical design engineers also weigh in on package planning and DFT scan-chain ordering at the block level.

The employer roster reads heavy on companies that ship volume silicon: Qualcomm, Apple, Broadcom, Marvell, MediaTek, plus a long tail of AI and networking chip startups that need clean tapeouts at 7nm or below. Many physical design roles overlap closely with RTL design roles at the team level, particularly during integration phases when timing pressures push changes back up the flow.

Compensation in Silicon Valley for senior physical design engineers lands at $180K to $260K total comp, with base typically in the $150K to $200K range and equity making up the rest. At staff or principal levels at Apple, Qualcomm, or the hyperscalers, total comp routinely clears $300K. For level-by-level numbers, the salary guide tracks current ranges by region.

Remote physical design roles remain less common than RTL or verification. The work depends on compute farms running EDA licenses, which is harder to support fully remotely than file-based simulation. Hybrid setups are now standard. Fully remote postings exist at startups using cloud EDA platforms, but they remain a minority of the listings.

Place-and-route specialist roles and STA engineering positions are common adjacent specializations. Engineers regularly pivot between physical design generalist roles and a deeper specialty as they get more senior.

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FAQ

What tools are most important for physical design engineer jobs?

Cadence Innovus and Synopsys IC Compiler 2 (ICC2) are the dominant P&R tools. Synopsys PrimeTime handles STA. Siemens Calibre and Synopsys IC Validator cover physical verification. Most postings ask for production experience in one P&R tool plus one verification tool; running both Innovus and ICC2 in the same role is unusual.

What is the difference between physical design and layout engineering?

Physical design engineers work at the block or chip level using automated PnR tools. Layout engineers manually draw transistor-level geometries for analog or memory cells. Physical design dominates digital ASIC workflows; layout engineering shows up in analog, mixed-signal, and memory teams.

Are physical design engineer jobs available remotely?

Less commonly than RTL or verification roles. PnR runs depend on compute farms and EDA license management, which is harder to support fully remotely. Hybrid setups are now standard at most companies. Fully remote physical design roles exist at startups using cloud EDA platforms, but they remain a minority.