STA/Timing Closure Lead

Job Title

STA/Timing Closure Lead

Role Summary

Lead development of STA and timing-closure solutions for very large-scale and 3D IC designs. Collaborate with R&D and customers to define product architecture, run backend timing flows on customer designs, and drive product improvements based on field results.

Role requires hands-on technical ownership of timing methodology and frequent customer engagements.

Experience Level

Senior-level; typically requires 10+ years of experience in STA and timing closure at tier-1 design houses.

Responsibilities

The role centers on designing timing-closure approaches, validating flows on customer designs, and communicating findings to product and research teams.

• Define timing-closure methodology for very large designs and 3D ICs in coordination with R&D.
• Run backend and STA flows on customer designs and validate solutions.
• Analyze timing results and propose fixes across synthesis, place-and-route, and interconnect.
• Share customer feedback with research and product teams to prioritize improvements.
• Serve as the in-house subject-matter expert on STA and timing closure.
• Engage directly with customers to deploy and refine timing solutions.

Requirements

Must-have skills and experience.

• 10+ years running STA and timing closure at tier-1 design houses.
• Proven experience closing timing at advanced process nodes.
• Hands-on experience with commercial synthesis and timing tools (e.g., Design Compiler, Fusion Compiler).
• Deep knowledge of STA methodologies, Liberty formats, and device characterization.
• Background in device physics at advanced nodes.
• Experience with die-to-die or chiplet-to-chiplet timing closure.
• Experience closing timing on 3D ICs, including TSV and interconnect timing.
• Interest and experience working directly with customers to shape products.

Nice-to-have:

• Familiarity with the broader implementation flow, including place-and-route.
• Experience using AI coding agents (e.g., Claude Code, Codex, OpenCode).
• Scripting experience in Python, Tcl, or Makefiles.

Education Requirements

Required: Bachelor's (BS) or Master's (MS) degree in Electrical Engineering, Computer Engineering, or a related technical field (as listed in the posting).

About the Company

Company: ChipAgents

Headquarters: San Jose, CA, United States

ChipAgents is a Series A startup developing agentic AI workflows for chip design and verification, leveraging generative AI and large language models to assist RTL design, simulation, and EDA workflows for semiconductor and cloud customers.