Senior/Principal Physical Design Engineer

Job Title

Senior/Principal Physical Design Engineer

Role Summary

Lead the physical implementation of complex SoCs and digital blocks from RTL to GDSII, ensuring performance, power, area, signal integrity, and manufacturability targets are met.

Work on the backend implementation flow (floorplanning, P&R, CTS, power planning, STA, and physical verification) and partner with architecture, RTL, analog, and verification teams. Provide technical leadership and mentor other engineers.

Experience Level

Senior — typically 7+ years of ASIC physical design experience (posting indicates ~7 to 15+ years depending on degree level).

Responsibilities

Deliver end-to-end physical implementation and drive physical design methodology improvements.

• Own RTL-to-GDSII execution for SoCs or complex digital blocks (floorplan, P&R, signoff).
• Manage floorplanning, bump planning, power grid design, and clock tree synthesis to meet PPA goals.
• Perform static timing analysis (STA) and drive timing closure and congestion resolution.
• Identify and fix EM/IR issues and address DRC/LVS violations during signoff flows.
• Automate flows and improve robustness using scripting (Tcl, Python, Perl).
• Collaborate with architects, frontend designers, and analog teams to ensure tapeout readiness.
• Define and propagate physical-design best practices and mentor junior engineers.

Requirements

Must-have technical skills and experience for the role.

• Minimum: substantial ASIC physical design experience (posting indicates 7+ years; exact requirement varies by role level).
• Proven tapeout experience in advanced nodes (examples: 7nm, 5nm, 3nm).
• Advanced proficiency with backend EDA tools (examples: Cadence Innovus, Tempus, Voltus, Pegasus, Calibre).
• Hands-on STA and physical verification experience; ability to resolve DRC/LVS and signoff issues.
• Expertise in physically aware synthesis, power domain analysis, and EM/IR mitigation.
• Scripting and automation skills (Tcl, Python, or Perl) to improve flow robustness.
• Nice-to-have: SoC-level experience, mentorship/technical leadership history, cross-functional integration with analog/IO teams.

Education Requirements

The posting references "depending on degree level" when describing years of experience but does not specify specific degrees (Bachelor's, Master's, PhD), fields of study, certifications, or explicit equivalent-experience language.

About the Company

Company: Celero Communications

Headquarters: Ottawa, Ontario, Canada

Designs and develops optical transceivers and ASIC solutions for next-generation optical modems, focusing on digital ASIC/RTL design, verification, and optical communication technologies.