Static Timing Analysis (STA) Methodology Engineer

Job Title

Static Timing Analysis (STA) Methodology Engineer

Role Summary

Lead STA methodology development and timing closure for advanced-node, high-performance, low-power ASIC/SoC designs. Own end-to-end STA flows (RTL-to-GDS), signoff correlation, timing optimization, and cross-functional coordination with logic, physical design, DFT, and EDA vendors.

Tenstorrent builds high-performance RISC-V CPU and AI platforms; this role contributes to production-grade timing methodologies across multiple IPs and products.

Experience Level

Mid-level (Level - Mid-Career). Guidance: approximately 5+ years of industry experience in STA/methodology; candidate level will be assessed during interview.

Responsibilities

Own and improve timing methodology and flows; enable signoff and scale methodologies across IPs and full-chip designs.

• Lead cross-functional timing efforts and act as the methodology owner across multiple IPs and projects.
• Develop, optimize, and maintain production STA flows and CAD utilities for RTL-to-GDS signoff.
• Perform and validate signoff STA (PrimeTime and related signoff flows), including noise, crosstalk, and OCV analysis.
• Drive timing correlation and closure strategies from synthesis through place-and-route and post-route ECO.
• Implement data-driven and ML-assisted techniques to prioritize timing risk and automate STA tasks.
• Collaborate with EDA vendors to influence tool behavior and resolve advanced-node timing challenges.
• Mentor engineers and document methodologies to improve team productivity and PPA/runtime efficiency.

Requirements

Core technical skills and production experience required to lead STA methodology and timing closure.

• Must-have: Deep hands-on STA experience and strong debugging skills for timing constraints and correlation.
• Proven experience with Synopsys PrimeTime and related signoff tools (e.g., PT-SI, PTPX, PT-ECO).
• Experience across RTL-to-GDS flow: early timing estimation, synthesis/place-and-route timing optimization, signoff criteria, and post-route ECO execution.
• Strong scripting skills and delivery of production-quality CAD utilities (Tcl, Python, and/or Perl).
• Experience improving PPA and runtime efficiency of STA flows and tooling at advanced technology nodes.
• Ability to work cross-functionally with logic, physical design, DFT teams, and EDA vendors to resolve complex timing issues.
• Nice-to-have: Experience applying data-driven or ML techniques to STA, and prior work on noise/crosstalk/variability modeling at advanced nodes.

This position requires the ability to access U.S. export-controlled technology; employment may be contingent on citizenship, permanent residency, or obtaining an export license.

Education Requirements

Bachelor's or Master's in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.

About the Company

Company: Tenstorrent

Headquarters: Austin, Texas, United States

Tenstorrent is a technology company focused on designing innovative computing solutions. They are known for their expertise in the development of advanced hardware, including ASICs and SoCs, aimed at enhancing performance and efficiency in various applications.