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Senior/Principal Full-Chip Physical Verification Engineer

Celero Communications
July 29, 2026
Full-time
On-site
San Jose, California, United States
$150,000 - $250,000 USD yearly
Physical Design Jobs, Level - Senior

Job Title

Senior/Principal Full-Chip Physical Verification Engineer

Role Summary

Join the Physical Design team to own full-chip physical verification on advanced process nodes. You will lead verification execution, ensure tapeout readiness, and collaborate with analog and physical design teams to resolve manufacturability and performance issues.

Experience Level

Senior-level. The posting requests 7+ years of experience in full-chip verification and tapeout execution.

Responsibilities

Lead and execute full-chip physical verification activities and coordinate across teams to deliver tapeout-ready designs.

  • Lead full-chip physical verification efforts and own execution plans and schedules.
  • Run and analyze DRC/ERC/LUP/PERC results; ensure design clean-up and manufacturability.
  • Work with analog IP and physical design teams to ensure clean IP delivery and integration.
  • Provide early guidance on corner-case requirements, floorplan constraints, and hierarchy strategy.
  • Participate in tapeout readiness reviews and drive accountability for quality and milestones.
  • Develop and maintain verification flows for block and chip-level signoff.

Requirements

Must-have technical skills and experience for immediate impact; preferred skills listed separately.

  • 7+ years of experience with full-chip verification and multiple tapeouts.
  • Hands-on experience with physical verification tools (ICV or Calibre).
  • Ability to assemble and maintain flows for block- and chip-level verification.
  • Strong floorplanning expertise to prevent DRC/LVS issues and enable clean integration.
  • Experience running and interpreting DRC/ERC/LUP/PERC analyses and driving fixes.
  • Proven cross-functional collaboration with analog, block, and chip teams to meet schedule and quality goals.
  • Preferred: automation skills (Tcl, Python, shell) and experience in advanced nodes (7nm/5nm/3nm).

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering or a related field.


About the Company

Company: Celero Communications

Headquarters: Ottawa, Ontario, Canada

Designs and develops optical transceivers and ASIC solutions for next-generation optical modems, focusing on digital ASIC/RTL design, verification, and optical communication technologies.

Celero Communications logo

Date Posted: 2026-07-22