Senior Mixed-Signal Verification Engineer

Job Title

Senior Mixed-Signal Verification Engineer

Role Summary

Lead mixed-signal verification for digital-to-analog interfaces on Arago's SoCs. Work across analog, RTL, architecture, firmware, and verification teams to define methodology, create verification plans, and drive verification to sign-off.

Experience Level

Senior — expects an experienced engineer with substantial ASIC/SoC verification background.

Responsibilities

You will own mixed-signal verification activities from methodology through tape-out for digital-to-analog interfaces.

• Define and own mixed-signal verification methodology and verification plans for DAC/ADC and related interfaces.
• Build and maintain verification environments at block, subsystem, and SoC levels.
• Develop tests, assertions, checkers, scoreboards, and functional coverage.
• Verify digital control/configuration of analog/mixed-signal circuitry across normal operation, corners, and error conditions.
• Run regressions, analyze coverage, debug failures, and drive closure to sign-off.
• Develop or integrate behavioral and real-number models for mixed-signal simulation.
• Collaborate closely with analog, RTL, architecture, firmware, and SoC verification teams to resolve interface issues.

Requirements

Key must-have skills and practical experience for the role.

• Hands-on ASIC/SoC verification experience.
• Proven experience verifying mixed-signal blocks or digital-to-analog / analog-to-digital interfaces.
• Strong SystemVerilog skills and practical experience with UVM or equivalent verification methodology.
• Experience building verification environments and developing tests, assertions, scoreboards, and functional coverage.
• Good understanding of digital design fundamentals and basic analog/mixed-signal concepts.
• Strong debugging skills across RTL, models, clocks, resets, configuration, and analog behavior.
• Scripting and automation experience (preferably Python, Tcl, shell, or similar).
• Proficient English communication skills.

Nice-to-have:

• Experience with high-speed PHY interfaces (PCIe, DDR/LPDDR, UCIe, SerDes, USB, CXL) and their initialization/link training.
• Experience with real-number modeling (SystemVerilog RNM, wreal, Verilog-AMS) or equivalent techniques.
• Experience integrating behavioral models of analog/PHY components into digital verification environments.
• SoC-level integration and verification of complex interface IP; low-power verification (UPF) experience.
• Track record driving coverage closure and tape-out for complex IP or SoC verification efforts.

Education Requirements

Not specified.

About the Company

Company: Arago

Arago is an AI and computer hardware startup (founded 2024) developing AI-driven semiconductor and photonics solutions. The company brings together engineers and researchers in photonics, electronics, software, mathematics, and machine learning to accelerate prototype-to-silicon development across hubs in France, North America, and Israel.