Sr. Director of Design Engineering

Job Title

Sr. Director of Design Engineering

Role Summary

Lead teams delivering complex ASIC designs from floorplan through physical verification. Drive development of deep sub-micron, low-power and high-performance physical design methodologies and flows, coordinate with EDA vendors, and work with sales and management to meet customer specifications, schedules, and budgets. Multiple positions available; telecommuting 1–2 days per week.

Experience Level

Senior — title indicates senior leadership. Experience guidance from the posting: 24 months (2 years) of relevant ASIC backend and low-power physical design experience in 7nm and below process technologies.

Responsibilities

Primary responsibilities include technical leadership, methodology development, vendor coordination, and cross-functional collaboration.

• Manage development of complex ASIC designs including chip-level floorplanning, placement & route, clock implementation, static timing analysis, and physical verification.
• Define and implement physical design methodologies and flows for deep sub-micron, low-power, high-performance designs; combine auto P&R and custom flows as needed.
• Coordinate with EDA vendors to test and evaluate new tool features; analyze compatibility, stability, and PPA and propose improvements.
• Collaborate with sales and product teams to interpret ASIC specifications, estimate die size, floorplan, schedule, and resource needs, and recommend solutions.
• Ensure projects comply with company standards, meet schedule and budget targets, and deliver required technical quality.

Requirements

Must-have experience and skills. Academic degree requirements are shown under Education Requirements below.

• Minimum 24 months of experience in ASIC backend design using 7nm and below process technologies, including floorplanning, P&R, clock implementation, STA, and physical verification with Synopsys, Cadence, or Siemens tools.
• Minimum 24 months of experience in low-power physical design and developing flows that minimize power while meeting performance targets.
• Minimum 24 months of experience estimating die-size, floorplan, schedule, and resource needs from customer specifications and recommending technical solutions.
• Proven ability to define, document, and validate physical implementation methodology and flows.
• Availability to travel to China approximately twice per year (total 1–4 months annually).
• Management experience and strong cross-functional communication skills to engage with sales, EDA vendors, and senior management.

Education Requirements

Bachelor's degree in Electrical Engineering or a related field required (foreign degree acceptable).

About the Company

Company: Alchip Technologies

Headquarters: Hsinchu, Taiwan

Fabless semiconductor company providing ASIC design, turnkey services, and high-performance silicon solutions for complex system-on-chip (SoC) applications, with global engineering and customer support.