F

Senior Analog IC Design Engineer — IVR Architecture Team

Ferric
July 21, 2026
Full-time
On-site
New York, NY, United States
ASIC Design Jobs, Level - Senior

Job Title

Senior Analog IC Design Engineer — IVR Architecture Team

Role Summary

Join Ferric's IVR Architecture Team to design and verify integrated voltage regulator (IVR) systems and analog IP for high-efficiency power delivery in applications from AI processors to wearables. The role focuses on system architecture, simulation, modeling, and coordination across design, applications, and test teams.

Experience Level

Senior. Specific years-of-experience guidance not specified.

Responsibilities

Primary responsibilities focus on system-level IVR architecture and delivery of analog IP to meet performance targets.

  • Define and drive system architecture to meet targets for efficiency, density, transient response, input supply rejection, and reference tracking.
  • Derive specifications for sub-blocks from system-level requirements.
  • Develop and maintain system-level models and simulations for power conversion and control solutions.
  • Perform system-level simulation, verification, and bench-correlation for performance prediction.
  • Design, simulate, and layout analog IP relevant to IVRs as needed.
  • Coordinate across design, applications, and test teams to champion system-level performance goals.

Requirements

Must-have technical skills and practical experience required for successful execution of the role. Nice-to-have items are listed separately.

  • Must-have: Strong knowledge of control theory and stability analysis.
  • Strong knowledge of switching power converter design and experience with high switching frequency IVRs.
  • Deep knowledge of CMOS analog circuit design and experience with custom IC design flows and tools.
  • Experience with mixed-signal verification methodologies and Monte Carlo analysis.
  • Experience with EDA tools and flows: schematic capture, SPICE simulation, parasitic extraction, LVS/DRC; familiarity with Cadence Virtuoso and related toolchains.
  • Experience with bench-level validation, characterization, and debug of ICs and IC sub-systems.
  • Proficiency in scripting and hardware description languages such as Verilog, Verilog-AMS, Python, Perl, Tcl, Cadence Skill, MATLAB, etc.
  • Nice-to-have: Experience with exotic semiconductors; deeper digital circuit design background; electromagnetics simulators experience.

Education Requirements

Requires an MSEE (Master of Science in Electrical Engineering) with analog design experience (explicitly stated in the source). No alternative "equivalent experience" language was provided.


About the Company

Company: Ferric

Headquarters: New York, NY, USA

New York City–based startup developing thin‑film magnetic inductors integrated with CMOS to improve power delivery for integrated circuits and electronic assemblies; designs integrated voltage regulators for high‑power SoCs and ultra‑low‑power mobile platforms.

Ferric logo

Date Posted: 2026-07-19