Principal Design Verification Engineer – CPU Subsystem Power Management

Job Title

Principal Design Verification Engineer – CPU Subsystem Power Management

Role Summary

Lead verification of CPU-subsystem power-management features across unit, subsystem, and SoC contexts. Define verification strategy, identify integration and microarchitectural risks, and drive signoff-quality closure for DVFS, retention, clock/reset sequencing, power gating, and related interactions.

This principal technical role coordinates architecture, RTL, formal, DV, and performance teams and raises verification methodology and infrastructure across the organization.

Experience Level

Senior-level — Principal. Typical requirement: 12+ years of relevant functional verification experience at a principal or equivalent level.

Responsibilities

Key responsibilities include planning, execution, and technical leadership for power-management verification:

• Lead verification planning and execution from unit level through subsystem integration and signoff for power-management features.
• Define verification strategies, test plans, assertions, checkers, coverage models, and closure criteria for power-state transitions, clock/reset sequencing, retention behavior, DVFS, warm-reset flows, and multi-domain interactions.
• Drive verification across multiple bench contexts, including CoreIP, PMC unit-level, and broader PM unit and uncore environments.
• Own high-value stress, corner-case, and long-run scenarios; lead failure analysis and root-cause debug across spec, RTL, and infrastructure.
• Apply appropriate methods (simulation, formal, power-aware verification, emulation) for subsystem-level signoff.
• Contribute reusable methodology, automation, and DV infrastructure to improve quality and productivity.
• Mentor engineers and provide technical leadership for difficult subsystem-level debug and closure challenges.
• Define signoff expectations suitable for data-center-grade CPU subsystems.

Requirements

Must-have skills and experience:

• 12+ years of relevant experience in CPU, subsystem, SoC, or ASIC functional verification at a principal level.
• Deep domain experience in CPU-subsystem power-management verification: clock/reset behavior, power-state transitions, retention, gating, and multi-domain interactions.
• Hands-on SystemVerilog-based verification expertise: assertions, checkers, coverage strategy, and complex debug workflows.
• Proven ability to translate architectural intent into an effective verification strategy and execution plan targeting signoff quality.
• Software/scripting skills (Python or similar) for DV infrastructure and automation.
• Experience with formal verification, power-aware simulation, or emulation is preferred.
• Strong technical communication and cross-functional collaboration skills.
• Ability to work in the United States and pass background and export-control checks as required.

Education Requirements

BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field (as stated in the posting).

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.