Principal Design Verification Engineer – CPU Core Hardware Prefetch

Job Title

Principal Design Verification Engineer – CPU Core Hardware Prefetch

Role Summary

Lead verification strategy and execution for hardware prefetch in a high-performance out-of-order CPU core. Own unit- and core-level verification, cross-team coordination with architecture, RTL, performance, software, and verification teams, and drive signoff quality.

Primary focus areas include prefetch training and stream detection/replacement, request generation and replay/kill behavior, issue-queue and cache interactions, CSR configurability, and coverage-driven verification.

Experience Level

Senior — Principal-level role. Typically requires 12+ years of relevant CPU/SoC functional verification experience.

Responsibilities

Lead technical verification efforts, define strategy, and mentor engineers. Key responsibilities include:

• Plan and execute verification for CPU hardware prefetch across unit and core integration levels; drive coverage closure and signoff readiness.
• Define verification strategy, test plans, checkers, scoreboards, assertions, stimulus strategies, and coverage models for advanced prefetch microarchitecture.
• Verify prefetch behaviors: stream allocation/replacement, training from demand requests, prefetch generation, replay/kill behavior, and issue-queue interactions.
• Validate runtime configurability via CSRs and verify interactions with L1/L2 caches, MSHRs, and other core traffic.
• Develop tests and methodologies for corner cases such as misconfirmation, untraining, queue unavailability, throttling, page-boundary behavior, and multi-stream scenarios.
• Apply simulation, formal, emulation, and performance-oriented validation where appropriate for high-risk or hard-to-observe behaviors.
• Lead failure analysis and root-cause debug across specification, RTL, test content, assertions, and verification infrastructure.
• Mentor engineers and shape reusable verification approaches, infrastructure, and methodology for future CPU core generations.

Requirements

Must-have skills and experience:

• 12+ years of CPU/core or SoC functional verification experience with principal-level responsibility.
• Direct experience with out-of-order CPU core verification and strong CPU microarchitecture knowledge.
• Deep expertise in hardware prefetch or memory-subsystem verification and ability to translate architectural intent into verification plans.
• Strong verification methodology: test planning, stimulus generation, failure analysis, coverage analysis, and coverage closure.
• Strong debug skills and software/scripting fundamentals for building scalable DV infrastructure, automation, and analysis workflows.
• Strong understanding of CPU memory behavior, including ordering-sensitive interactions and cache-hierarchy effects.
• Experience with formal verification, emulation, or other acceleration techniques (preferred).
• Proven technical leadership, mentoring, and cross-team collaboration skills.
• 8+ years direct experience on memory management verification (MMU/IO-MMU) — preferred.

Education Requirements

BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.