RTL/PD Design Engineer - Tapeout & Microarchitecture
Normal ComputingJob Title
RTL/PD Design Engineer - Tapeout & Microarchitecture
Role Summary
Responsible for owning RTL from microarchitecture through synthesis and backend to produce fab-ready GDSII tapeouts. Work closely with architecture, verification, RTL, and physical-design teams to deliver robust silicon.
Experience Level
Mid-level. Years of experience not specified.
Responsibilities
Primary responsibilities include end-to-end RTL and backend delivery and cross-team collaboration.
- Own RTL design from microarchitecture through synthesis, place-and-route, and tapeout.
- Write and maintain synthesizable SystemVerilog.
- Drive synthesis and backend flows to produce GDSII tapeouts.
- Collaborate closely with architecture, verification, and physical design teams to meet timing, area, and power targets.
- Support post-silicon characterization and debug as needed.
Requirements
Core qualifications and expectations.
Must-have:- Experience writing synthesizable SystemVerilog and owning RTL modules.
- Practical experience taking RTL through synthesis and backend to GDSII tapeout.
- Proven ability to coordinate with architecture, verification, RTL, and physical-design teams.
- Experience supporting post-silicon characterization or silicon bring-up.
- Not specified.
Education Requirements
Not specified.
About the Company
Company: Normal Computing
Headquarters: New York, NY, USA
Normal Computing develops software and hardware solutions for the semiconductor and AI infrastructure industries, specializing in ASICs for image and video diffusion inference and AI accelerators. The company focuses on architecture and microarchitecture of compute blocks, PE array design, ISA co-design, and FPGA prototyping.
