RTL Design Engineer

Job Title

RTL Design Engineer

Role Summary

Normal Computing is developing thermodynamic ASICs for energy-efficient AI inference. The RTL Design Engineer will design and verify synthesizable digital logic and own RTL from microarchitecture through tapeout, working closely with architects and physical designers in a hybrid, multi-site engineering organization.

Experience Level

Mid-level. No explicit years stated; the role expects engineers with production RTL and tapeout experience.

Responsibilities

The engineer will be responsible for end-to-end RTL development, verification, and tapeout support.

• Write and own synthesizable SystemVerilog RTL across datapath, control, and memory interfaces.
• Author and maintain functional verification environments (UVM, cocotb, formal methods as applicable).
• Translate high-level specifications into implementable microarchitectures with architects.
• Collaborate with physical design on timing closure, floorplanning constraints, and DFT.
• Develop and maintain simulation infrastructure, regression pipelines, and coverage closure flows.
• Participate in design reviews and contribute to architecture decisions.
• Support tapeout preparation, integration, and post-silicon bring-up.

Requirements

Key qualifications and practical skills required and preferred for successful candidates.

Must-have

• Production experience writing RTL in SystemVerilog and closing it through synthesis and place-and-route.
• Experience authoring verification environments using UVM, cocotb, formal tools, or equivalent.
• At least one tapeout in any process node or company size.
• Experience across both design and verification; comfortable owning both roles.
• Background in ASIC or SoC design and working on datapaths, pipelines, or custom logic.
• Strong debugging skills with simulators, waveforms, and formal counterexamples.
• Able to work directly with architects and physical designers.

Nice-to-have

• Experience at an AI chip company where design and verification were tightly coupled.
• Open-source RTL contributions (e.g., Chipyard, OpenTitan, CVA6).
• Familiarity with RISC-V or other open ISAs.
• Experience with AI-assisted RTL/EDA tooling or exposure to floorplanning and timing-driven RTL development.

Education Requirements

Not specified.

Compensation

Salary range reported: $205,000 - $285,000 per year, plus equity.

Accessibility

Normal Computing provides reasonable accommodations for applicants with disabilities; accommodation requests may be sent to accommodations@normalcomputing.com.

Equal Opportunity

Normal Computing is an Equal Opportunity Employer and considers qualified applicants without regard to legally protected characteristics.

About the Company

Company: Normal Computing

Headquarters: New York, NY, USA

Normal Computing develops software and hardware solutions for the semiconductor and AI infrastructure industries, specializing in ASICs for image and video diffusion inference and AI accelerators. The company focuses on architecture and microarchitecture of compute blocks, PE array design, ISA co-design, and FPGA prototyping.