Principal SerDes Design Engineer

Job Title

Principal SerDes Design Engineer

Role Summary

Lead architecture and design of high-speed SerDes transceivers for AI networking and optical connectivity. Responsible for system-level modeling, analog/mixed-signal circuit design, physical layout oversight, lab validation, and silicon-to-system performance optimization.

Work focuses on delivering higher bandwidth, lower power, and production-ready SerDes IP for next-generation AI infrastructure.

Experience Level

Senior-level; requires 10+ years of relevant SerDes design experience.

Responsibilities

Lead and execute SerDes IP development across architecture, design, verification, and delivery:

• Define architecture, specifications, and circuit topologies for next-generation SerDes.
• Develop system-level behavioral models (MATLAB, SystemVerilog, Verilog-A) to analyze link budgets, equalization strategies, and jitter budgeting.
• Design high-performance analog/mixed-signal circuits and critical blocks (RX/TX equalization: CTLE, DFE; high-speed PLLs; phase interpolators; DLLs; TDCs).
• Implement digitally assisted analog circuits, background calibration, and adaptive loops to improve power, performance, and area.
• Oversee physical layout to minimize parasitics, electromigration, and process variation impacts.
• Perform signal integrity and power integrity analysis to meet system-defined targets.
• Lead lab bring-up, debugging, characterization, and correlation of silicon measurements with simulation.
• Collaborate with cross-functional teams to integrate SerDes IP into SOCs and drive system-level optimizations.

Requirements

Must-have technical experience and skills:

• Proven track record taking high-speed SerDes designs to tape-out and volume production.
• Extensive experience with advanced process nodes (16/12nm, 7nm, 5nm, 3nm, 2nm).
• Hands-on lab bring-up, characterization, and debugging of high-speed designs.
• Expertise in system-level modeling and behavioral simulation tools (MATLAB, SystemVerilog, Verilog-A).
• Experience overseeing analog/mixed-signal layout and mitigating parasitics and process variation.
• Strong documentation, communication, and cross-functional collaboration skills.
• Nice-to-have: prior work on optical connectivity or digitally-assisted analog implementations.

Education Requirements

Master's degree and/or PhD in Electrical Engineering or a related technical field (as stated in source). Equivalent-experience language was not specified.

About the Company

Company: Celero Communications

Headquarters: Ottawa, Ontario, Canada

Designs and develops optical transceivers and ASIC solutions for next-generation optical modems, focusing on digital ASIC/RTL design, verification, and optical communication technologies.