Principal DFT Engineer

Job Title

Principal DFT Engineer

Role Summary

Responsible for defining and implementing Design-for-Test (DFT) architecture and flows for ASIC and SoC products. Partners with design, verification, physical design, product, and manufacturing teams to enable testability, manufacturing diagnostics, and production readiness.

Experience Level

Senior-level. Requires 8+ years of ASIC/SoC DFT experience.

Responsibilities

Primary responsibilities include designing and validating on-chip test solutions and supporting silicon validation and manufacturing readiness.

• Develop and implement DFT architecture for ASIC/SoC designs.
• Perform scan insertion, scan chain planning, and scan compression implementation.
• Generate and validate ATPG patterns and analyze fault coverage results.
• Implement and verify MBIST and other on-chip test features.
• Collaborate with RTL, verification, and physical design teams to ensure successful DFT integration.
• Support JTAG and boundary-scan implementation and debug.
• Drive DFT signoff activities and manufacturing test readiness.
• Participate in silicon bring-up, failure analysis, and yield improvement efforts.

Requirements

Must-have technical skills and experience:

• 8+ years of ASIC/SoC DFT experience.
• Strong understanding of scan, ATPG, fault models, and test coverage methodologies.
• Experience with tools such as Synopsys TestMAX/TetraMAX, DFT Compiler, Siemens Tessent, Cadence Modus, or equivalent.
• Knowledge of Verilog/SystemVerilog and digital design fundamentals.
• Experience in Linux and scripting (Python, Tcl, Perl, or Shell).
• Proven debugging skills and ability to work effectively in cross-functional teams.

Nice-to-have:

• Experience with advanced-node semiconductor technologies.
• Hands-on experience with MBIST, compression architectures, and JTAG.
• Knowledge of timing closure, physical design impacts, and low-power design techniques.
• Experience supporting silicon validation and manufacturing production ramps.

Education Requirements

Bachelors degree in Electrical Engineering, Computer Engineering, or a related technical field required.

About the Company

Company: Celero Communications

Headquarters: Ottawa, Ontario, Canada

Designs and develops optical transceivers and ASIC solutions for next-generation optical modems, focusing on digital ASIC/RTL design, verification, and optical communication technologies.