Power Integrity Engineer
Volantis SemiconductorJob Title
Power Integrity Engineer
Role Summary
Responsible for analysis and design of power-delivery networks (PDN) across chip and system levels — including rack/tray, package, die, and core. Collaborates with package architects, ASIC and microarchitecture teams to meet power-integrity, performance, and manufacturability targets on advanced-node devices.
Experience Level
Mid-level; typically 3–7 years of relevant power integrity or PDN experience preferred.
Responsibilities
Key responsibilities include:
- Analyze and design PDNs for high-TDP, large-die chips across package and die levels.
- Collaborate with package architects to select and place passives within given constraints.
- Work with ASIC and microarchitecture teams to achieve power-integrity goals given manufacturing and design constraints.
- Perform PDN simulation, modeling, and validation at die, package, board, and system levels.
- Identify and mitigate IR drop, noise, and thermal impacts on power delivery.
- Document design decisions, assumptions, and provide guidance for manufacturing handoff.
Requirements
Must-have skills and experience:
- Experience with large-die, high-TDP chip PDN analysis and design.
- Experience with advanced-node (7 nm and below) PDN analysis and design.
- Ability to collaborate effectively with package architects and ASIC/microarchitecture teams.
- Practical experience with PDN simulation and validation tools and workflows.
Nice-to-have:
- Experience with wafer-scale integration (WSI) systems.
- Board- and system-level PDN analysis and design experience.
- Low-voltage die PDN analysis and multi-voltage-domain PDN design experience.
- Experience with IVR-based PDN architectures.
Education Requirements
Not specified.
About the Company
Company: Volantis Semiconductor
Semiconductor hardware startup developing wafer-scale heterogeneous packages that integrate silicon and compound semiconductor dies for high-TDP AI platforms. Focus areas include advanced packaging design and process development, interposer technologies, thermal/mechanical challenges, and system co-design.
