Packaging Engineer, Flip Chip

Job Title

Packaging Engineer, Flip Chip

Role Summary

Develop and transfer flip chip package and assembly processes for advanced semiconductor devices (2.5D/3D/chiplet/fan-out/flip-chip). Work across package design, substrate integration, assembly, reliability qualification, and failure analysis toward robust, high-volume production.

Experience Level

Mid-level. Specific years of experience not stated.

Responsibilities

Key responsibilities include process development, integration, and failure analysis for flip chip assemblies.

• Develop and optimize flip chip attach processes: bump formation, placement, reflow, and underfill.
• Define and manage bump metallurgy stacks and substrate pad finishes (e.g., Cu pillar, SnAg, micro-bumps).
• Drive package integration from die to substrate, ensuring alignment, coplanarity, and yield optimization.
• Evaluate and mitigate assembly risks: warpage, non-wet opens, voiding, head-in-pillow, and interconnect defects.
• Collaborate with substrate vendors, OSATs, and internal teams to define design rules (pad pitch, bump pitch, keep-outs, stack-ups).
• Lead development of reflow profiles, flux selection, cleaning, and underfill dispense/cure processes.
• Perform root-cause analysis of assembly and reliability failures using cross-sectioning, SEM, CSAM, and related techniques.
• Support reliability qualification testing (thermal cycling, drop, mechanical shock, power cycling).
• Work cross-functionally with design, reliability, thermal, and manufacturing teams to move packages to high-volume production.

Requirements

Must-have technical skills and abilities for the role.

• Proven experience in flip chip packaging and assembly processes for semiconductor devices.
• Deep understanding of bumping technologies and UBM/metallization systems (solder bumps, Cu pillar, micro-bumps).
• Experience with underfill materials, dispense techniques, flow behavior, and cure processes.
• Knowledge of thermo-mechanical behavior in flip chip assemblies (CTE mismatch, warpage, solder fatigue).
• Hands-on failure analysis and reliability testing experience (cross-sections, SEM, CSAM, thermal cycling).
• Experience working with OSATs and suppliers to develop and transfer assembly processes into production.
• Strong problem-solving skills for debugging yield and reliability issues in manufacturing environments.

Nice-to-have / preferred:

• Experience with III-V or photonics packaging and precision chip attach.
• Experience with advanced packaging (2.5D interposers, 3D stacking, chiplets, CoWoS-like architectures).
• Familiarity with fine-pitch micro-bump, hybrid bonding, and photonics bill-of-materials (clear adhesives, mold compounds).
• Experience integrating high-power/high-TDP devices with tight warpage and thermal constraints.
• Exposure to thermo-mechanical modeling or collaboration with simulation teams.
• Understanding of system-level interactions (PCB attach, second-level interconnect reliability).

Education Requirements

Not specified.

About the Company

Company: Volantis Semiconductor

Semiconductor hardware startup developing wafer-scale heterogeneous packages that integrate silicon and compound semiconductor dies for high-TDP AI platforms. Focus areas include advanced packaging design and process development, interposer technologies, thermal/mechanical challenges, and system co-design.