Packaging Engineer - Bump Interconnect

Job Title

Packaging Engineer - Bump Interconnect

Role Summary

Lead development of bump interconnects for advanced semiconductor packages (2.5D/3D/chiplet/fan-out). The role covers ubump (micro-bump) and C4 bump metallurgy, RDL process and design, capture pad rules, OSAT engagement, reliability, failure analysis, and cross-functional support through package productization.

Experience Level

Mid-level engineer. The posting requests an experienced engineer; typical candidates will have multiple years of semiconductor packaging experience (3+ years).

Responsibilities

Primary responsibilities include process development, design-rule definition, qualification, and reliability support for bump interconnects and RDL.

• Own end-to-end bump interconnect development for ubump (micro-bump/Cu pillar) and C4 processes, including formation and reflow for mass reflow, TCB, and LAB attach.
• Define bump metallurgy stacks, UBM selection, and pad finish specifications for chip-side and interposer/substrate capture pads.
• Develop design rules for pitch, bump diameter, standoff height, keep-outs, and land pad geometry for chip and capture pads.
• Lead RDL process development: Cu electroplating, via fills, seed/photolithography, pad finishes, and RDL design rules for line/space and via geometry.
• Collaborate with OSATs and bumping foundries to qualify processes and manage process transfer into production.
• Identify and mitigate assembly risks (non-wet opens, voiding, head-in-pillow, IMC growth, joint fatigue) across ubump and C4.
• Perform failure analysis and root-cause investigations using cross-sectioning, SEM, CSAM, and related techniques.
• Support reliability qualification (thermal cycling, drop, mechanical shock, power cycling) and work cross-functionally with design, reliability, thermal, and manufacturing teams.

Requirements

Must-have technical skills and experience required to perform the role; preferred items listed separately.

• Must-have: Proven experience with ubump (Cu pillar/micro-bump) and C4 bumping processes for semiconductor devices.
• Must-have: Deep understanding of bump metallurgy (UBM stacks, solder alloy systems such as SnAg), IMC formation and growth, and impacts on joint reliability.
• Must-have: Practical experience with RDL plating processes (Cu electroplating, seed layer, photoresist patterning), via fills, and RDL design rules.
• Must-have: Knowledge of thermo-mechanical behavior in bump assemblies (CTE mismatch, warpage, solder fatigue) and reliability risks for ubump and C4.
• Must-have: Hands-on failure analysis and reliability testing experience (cross-sections, SEM, CSAM, thermal cycling).
• Must-have: Experience working with OSATs and suppliers to develop and transfer assembly processes to production; strong problem-solving skills for manufacturing yield and reliability issues.
• Nice-to-have: Experience with III-V or photonics packaging, fine-pitch micro-bump or hybrid bonding, 2.5D/3D/chiplet architectures, high-power device integration, or thermo-mechanical modeling collaboration.

Education Requirements

Not specified.

About the Company

Company: Volantis Semiconductor

Semiconductor hardware startup developing wafer-scale heterogeneous packages that integrate silicon and compound semiconductor dies for high-TDP AI platforms. Focus areas include advanced packaging design and process development, interposer technologies, thermal/mechanical challenges, and system co-design.