Memory Architect

Job Title

Memory Architect

Role Summary

The Memory Architect will design and deliver Thermo In-Memory Computing memory systems for AI inference, translating novel memory primitives into silicon. You will work with silicon engineering, analog, physical design, and microarchitecture teams to define memory architecture, interfaces, and tapeout plans.

Goal: enable 100–1000× improvements in AI inference performance by rethinking memory microarchitecture and integration.

Experience Level

Mid-level. The role expects an experienced memory engineer; no specific years-of-experience were stated.

Responsibilities

Own memory microarchitecture, interfaces, and delivery from PDK acquisition through test-chip tapeout and production.

• Define processing-in-memory architecture, array organization, read/write paths, and decoder circuitry to enable in-memory compute.
• Architect internal datapaths, segmented buses, and on-die fabrics to move data between arrays and logic.
• Specify power distribution, budgets, thermal limits, redundancy, and ECC to meet performance and yield targets.
• Manage PDK access and fab engagements; plan test chips, shuttle/tapeout schedules, and silicon bring-up.
• Set requirements for primitive device libraries and partner with analog engineers on drivers and write circuits.
• Define external memory interfaces and controller/timing implications (e.g., SERDES, PCIe, Ethernet, DDR5, HBM-class interfaces).
• Oversee SPICE, analytical, and cycle-level modeling; validate workload-level PPA improvements.
• Own technical relationships with manufacturers and drive architectural trade-offs toward manufacturable solutions.

Requirements

Must-have technical skills and experience required to perform the role:

• Substantial experience in memory architecture or circuit design at a memory supplier or memory-centric compute company.
• Deep understanding of memory array physics and bitcell types (SRAM 1T/3T/6T/8T, DRAM), sensing, timing, retention, and reliability.
• Hands-on experience with embedded or random-access memory technology, PDKs, and developing memory test chips through tapeout.
• Ability to work from SPICE-level circuit behavior to architecture-level performance and power models; proficiency in scripting/programming for modeling (Python, C, or C++).
• Experience with RTL/SystemVerilog to model dataflow and specify compute block requirements.
• Experience with memory interface types and controller timing considerations.
• Strong written and verbal communication skills and ability to collaborate across disciplines.

Nice-to-have:

• Experience with process-in-memory, near-memory compute, or non-volatile memory technologies.
• DRAM technology experience (including eDRAM) or publications at ISSCC, VLSI, IEDM, ISCA.
• Existing relationships with semiconductor manufacturers.

Education Requirements

Not specified.

About the Company

Company: Normal Computing

Headquarters: New York, NY, USA

Normal Computing develops software and hardware solutions for the semiconductor and AI infrastructure industries, specializing in ASICs for image and video diffusion inference and AI accelerators. The company focuses on architecture and microarchitecture of compute blocks, PE array design, ISA co-design, and FPGA prototyping.