Physical Design & Signoff CAD Engineer

Job Title

Physical Design & Signoff CAD Engineer

Role Summary

Join the Infra Silicon Physical Design CAD team to develop and scale RTL-to-GDSII implementation and signoff flows for large, high-performance SoCs. The role focuses on advancing implementation and signoff methodology, building CAD infrastructure, and creating automation to make flows fast, reproducible, and scalable across designs.

Experience Level

Mid-level (typically 2+ years in physical design implementation and/or CAD methodology)

Responsibilities

Own and improve the implementation and signoff flows and supporting infrastructure for physical design and tapeout.

• Develop, deploy, and maintain end-to-end RTL-to-GDSII implementation flows: synthesis, floorplanning, placement, CTS, routing, and PPA optimization.
• Own and improve signoff methodology: static timing analysis, electromigration/IR drop analysis, physical verification, power analysis, logic equivalence checking, and SDC/UPF quality checks.
• Support active tapeout programs, debug flow and signoff issues, and drive issues to closure with design and STA teams.
• Build and extend CAD infrastructure: flow execution harnesses, run-tracking and QoR dashboards, and design release/version control systems.
• Develop scalable, AI-assisted tooling to automate flow setup, triage, QoR analysis, and optimization decisions.
• Qualify new EDA tool versions, foundry collateral, and reference methodologies.
• Document methodology and enable designers through training, office hours, and support.
• Collaborate across CAD, physical design, and silicon partner teams across multiple sites and time zones.

Requirements

Key technical skills and experience required and desirable for the role.

Must-have

• 2+ years of experience in physical design implementation and/or CAD methodology development.
• Working knowledge of the overall RTL-to-GDSII physical design flow.
• Hands-on experience with implementation flows: synthesis, place-and-route, and PPA optimization.
• Experience with signoff flows such as static timing analysis, electromigration/IR drop analysis, physical verification, power analysis, logic equivalence checking, and SDC/UPF quality checks.
• Scripting and automation experience applied to EDA flows (e.g., Tcl, Python).
• Experience collaborating with design teams and debugging flow issues through to resolution.

Nice-to-have

• Hands-on tapeout experience on leading-edge process nodes.
• Experience building CAD infrastructure: flow execution harnesses, QoR/run dashboards, and design release/version control systems.
• Experience developing scalable systems that apply AI/ML to EDA or engineering workflows.
• Experience working directly with EDA vendors and foundry partners on tool and collateral qualification.
• Breadth across both implementation and signoff stages and supporting large, multi-site SoC programs.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering, or equivalent practical experience.

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.