Link Validation Engineer
Volantis SemiconductorJob Title
Link Validation Engineer
Role Summary
Work on design validation testing (DVT) and bring-up of core optical links and PHYs. The role focuses on test development, hardware bring-up, measurement, and debugging of both electrical and optical PHY systems.
You will collaborate with PHY designers, system engineers, and test teams to verify performance, diagnose failures, and provide design feedback to improve silicon and optical subsystems.
Experience Level
Mid-level. Specific years of experience not stated; role expects hands-on validation and bring-up experience with PHYs and optical links.
Responsibilities
Primary responsibilities include validation, bring-up, and test engineering for optical link PHYs.
- Plan and execute DVT and bring-up activities for optical links and PHY hardware.
- Develop and run test cases to measure link performance (BER, jitter, TDECQ, etc.).
- Debug electrical and optical PHY issues using laboratory instruments and test fixtures.
- Provide actionable design feedback to PHY and electro-optic design teams.
- Collaborate with cross-functional teams to reproduce field issues and verify fixes.
- Document test procedures, results, and failure analyses.
Requirements
Must-have technical skills and practical experience for successful candidates.
- Hands-on experience with bring-up and DVT of optical links and PHYs.
- Deep understanding of PHY systems (electrical and optical) and optical link metrics (TDECQ, jitter, BER).
- Practical experience contributing to PHY design and validation; experience with electro-optic PHYs is preferred as a must-have where indicated.
Nice-to-have:
- Experience with clock-forwarded optical links.
- Experience with copper SERDES system bring-up as well as optical PHY bring-up.
- Familiarity with wide and slow optical architectures.
Education Requirements
Not specified.
About the Company
Company: Volantis Semiconductor
Semiconductor hardware startup developing wafer-scale heterogeneous packages that integrate silicon and compound semiconductor dies for high-TDP AI platforms. Focus areas include advanced packaging design and process development, interposer technologies, thermal/mechanical challenges, and system co-design.
