Hardware Engineer, Architect

Job Title

Hardware Engineer, Architect

Role Summary

Define the silicon and system microarchitecture for a custom mixed-signal AI compute platform focused on extreme energy efficiency for LLM and diffusion-model inference. Lead hardware/software co-design, translate workloads into microarchitectural specifications, and coordinate with compiler, RTL, analog, and FPGA teams to maximize throughput-per-watt on real workloads.

Experience Level

Senior-level engineer; substantial prior experience in architecture or microarchitecture of high-performance digital systems is expected. No specific years-of-experience stated.

Responsibilities

You will own microarchitecture decisions, workload translation, and pre-silicon validation strategy to deliver production-ready designs.

• Define compute-block and tile microarchitecture (PE arrays, datapaths, pipeline stages) with a focus on PPA (power, performance, area).
• Translate algorithm and workload behavior (transformers, KV-cache, attention, diffusion flows) into hardware structures and unambiguous microarchitecture documents for RTL teams.
• Drive full-stack PPA tradeoffs across algorithms, memory hierarchy, on-chip interconnect, and physical constraints; justify decisions with models and data.
• Co-design ISA and programming model with the compiler lead to align microarchitecture and software abstractions.
• Direct prototyping and pre-silicon validation strategy; partner with FPGA engineers for block-level de-risking prior to tapeout.
• Develop and maintain performance models and simulation workflows; evaluate design choices before RTL implementation.

Requirements

Must-have skills and experience required to perform the role; listed concisely.

• Must-have: Proven experience shaping microarchitecture or architecture of AI accelerators, high-performance compute engines, or similarly complex digital systems.
• Must-have: Ability to translate workload profiles into datapath widths, pipeline stages, memory hierarchy, and area/power estimates.
• Must-have: Experience with simulation-driven architecture (cycle-accurate or analytical modeling) to drive design decisions before RTL.
• Must-have: Familiarity with quantization and reduced-precision inference techniques and their hardware implications.
• Must-have: Experience writing microarchitecture specifications and collaborating closely with RTL engineers through implementation.
• Must-have: Proficiency in Python or C++ for performance modeling and analysis; familiarity with SystemVerilog or equivalent RTL.
• Nice-to-have: FPGA prototyping experience, mixed-signal exposure, or prior publication/engagement with accelerator research.

Education Requirements

Degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience. PhD is welcome but not required; employer accepts equivalent work experience in lieu of formal credentials.

About the Company

Company: Normal Computing

Headquarters: New York, NY, USA

Normal Computing develops software and hardware solutions for the semiconductor and AI infrastructure industries, specializing in ASICs for image and video diffusion inference and AI accelerators. The company focuses on architecture and microarchitecture of compute blocks, PE array design, ISA co-design, and FPGA prototyping.