Formal Verification Engineer

Job Title

Formal Verification Engineer

Role Summary

Join the core product and research team to develop and operationalize formal verification workflows for AI-assisted semiconductor verification. Work closely with AI engineers, researchers, and EDA partners to codify property development, proof strategies, and counterexample analysis so AI agents can reason about RTL correctness.

This role focuses on applying formal methods and assertion-based verification to train and evaluate agentic AI systems used across IP and SoC verification tasks.

Experience Level

Mid-level. The posting does not specify years of experience.

Responsibilities

Primary responsibilities include developing formal properties, using formal tools on RTL, and creating materials to train and evaluate AI verification agents.

• Collaborate with AI engineers and researchers to model and codify formal verification workflows.
• Develop, refine, and debug SystemVerilog Assertions (SVA), assumptions, constraints, and coverage objectives.
• Use formal verification tools to analyze RTL, prove correctness, and identify functional bugs.
• Create reusable examples, design patterns, proof strategies, and edge cases to train AI agents.
• Help AI systems interpret specifications, generate properties, and debug counterexamples.
• Support benchmarking and evaluation of AI-assisted formal verification on IP and SoC tasks.
• Engage with customers, product, and research teams to translate verification pain points into automated workflows.
• Contribute to methodology for assertion-based verification, equivalence checking, connectivity checking, and coverage closure.

Requirements

Must-have skills and practical experience for successful performance in this role.

• Strong expertise in formal verification methodologies and signoff flows.
• Hands-on experience with JasperGold, VC Formal, Questa Formal, or equivalent formal tools.
• Deep knowledge of SystemVerilog Assertions and assertion-based verification; experience proving properties and debugging counterexamples.
• Familiarity with SAT/SMT-based reasoning and formal verification fundamentals.
• Experience with CDC, RDC, lint, and static verification methods and strong RTL design and microarchitecture understanding.
• Experience verifying production IPs, subsystems, or SoCs.
• Proficiency in Python, Tcl, or similar scripting for verification automation.
• Interest in applying AI/LLMs to hardware design and verification workflows.

Education Requirements

Not specified.

About the Company

Company: ChipAgents

Headquarters: San Jose, CA, United States

ChipAgents is a Series A startup developing agentic AI workflows for chip design and verification, leveraging generative AI and large language models to assist RTL design, simulation, and EDA workflows for semiconductor and cloud customers.