DSP - FEC Design Engineer

Job Title

DSP - FEC Design Engineer

Role Summary

Design and implement forward error correction (FEC) algorithms and models for high-speed optical communication systems intended for ASIC/optical modem implementations. Work within a cross-functional team (DSP, ASIC, firmware, verification) to move algorithms from simulation to hardware-efficient implementations.

Experience Level

Mid-level engineer. Specific years of experience not specified.

Responsibilities

Primary responsibilities include research, algorithm development, modeling, and collaboration to enable hardware implementation of FEC and related DSP functions.

• Research, develop, and evaluate FEC schemes (LDPC, staircase, product codes, etc.) for high-speed optical links.
• Design and optimize soft-decision FEC algorithms for high-throughput implementations.
• Model and simulate FEC performance, including interactions with DSP blocks and channel impairments.
• Develop floating-point and fixed-point simulation models and bit-/cycle-accurate models for ASIC implementation and verification.
• Analyze trade-offs: coding gain, latency, throughput, and implementation complexity.
• Collaborate with DSP, ASIC, firmware, and verification teams to ensure efficient hardware realization.
• Document algorithm designs, simulation results, and implementation notes.

Requirements

Must-have technical skills and experience, plus a short list of desirable qualifications.

• Must-have: Strong theoretical background in coding theory, digital communications, and error-correction algorithms.
• Must-have: Experience developing and evaluating high-performance FEC algorithms for high-speed communication systems.
• Must-have: Experience building simulation models (floating-point and fixed-point) and bit-/cycle-accurate models for verification and ASIC targets.
• Must-have: Programming skills for algorithm implementation and simulation (C/C++, Python, MATLAB or similar).
• Must-have: Experience evaluating BER, coding gain, decoder complexity, and implementation trade-offs.
• Nice-to-have: Familiarity with DSP algorithms for communications and end-to-end system modeling.
• Nice-to-have: Experience with hardware description languages and hardware implementation considerations (Verilog, VHDL, ASIC flow).
• Nice-to-have: Experience with version control systems (GitHub) and working in cross-functional teams; industry experience preferred.

Education Requirements

Master's or Ph.D. in Electrical Engineering, Mathematics, Computer Engineering, or a related technical field is listed as preferred.

About the Company

Company: Celero Communications

Headquarters: Ottawa, Ontario, Canada

Designs and develops optical transceivers and ASIC solutions for next-generation optical modems, focusing on digital ASIC/RTL design, verification, and optical communication technologies.