SoC/ASIC Design Verification Engineer

Job Title

SoC/ASIC Design Verification Engineer

Role Summary

As a SoC/ASIC Design Verification Engineer at zeroRISC you will develop and verify security-sensitive silicon from architecture through tapeout and silicon validation. You will produce verification environments, test plans, and verification collateral while coordinating with design, software, system, and silicon validation teams.

You will work on products that emphasize hardware-rooted security and engage with external customers and the open-source silicon community as needed.

Experience Level

Mid-level — typically requires around 4 years of relevant design verification experience.

Responsibilities

Deliver verification solutions across chip and block levels and ensure functional, performance, security, and power requirements are met.

• Develop and execute simulation- and/or formal-based verification plans from test-plan definition to sign-off.
• Design, implement, and maintain UVM/SystemVerilog testbenches and verification environments.
• Build verification infrastructure for top-level and block-level integration.
• Write verification documentation, including test plans and status reports.
• Diagnose, debug, and resolve regression failures and design issues.
• Drive coverage closure and validate functional, performance, security, and power targets.
• Collaborate with architecture, RTL design, software, systems, silicon validation, and program management teams.
• Engage with customers to clarify verification requirements when necessary.

Requirements

Must-have technical skills and experience.

• ~4 years of experience with simulation-based verification methodologies and tools; strong knowledge of UVM and SystemVerilog, or experience with formal verification techniques.
• Experience developing and maintaining testbenches, test cases, and verification environments for ASIC/SoC projects.
• Proven ability to verify functionality, performance, security, and power across the full chip design lifecycle.
• Experience debugging regressions and driving defects and coverage to closure.
• Strong collaboration skills working across multi-disciplinary engineering teams.
• Familiarity with industry-standard verification tools and simulation flows.

Nice-to-have:

• Experience with security ASICs or accelerators (cryptography accelerators, GPUs) and computer architecture/memory subsystems.
• Experience verifying low-power designs.
• Scripting experience (Python) and automation for verification flows.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Science, or a related technical field, or equivalent practical experience. Preferred: Master's or PhD in Electrical Engineering, Computer Science, or a related technical field, or equivalent experience.

About the Company

Company: zeroRISC

Headquarters: Boston, MA, US

zeroRISC specializes in logic design, particularly in the fields of SoC and ASIC design verification. The company is based in Boston and focuses on delivering high-quality design solutions using Verilog and SystemVerilog.