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Digital IC Backend Design Engineer

Arago
August 27, 2026
Full-time
On-site
Paris, France
Physical Design Jobs, Level - Mid-Career

Job Title

Digital IC Backend Design Engineer

Role Summary

Implement digital ASIC designs from RTL to GDSII with a focus on physical implementation, timing closure, power and area optimization, and tapeout readiness. Work closely with RTL, DFT, and packaging teams in a small engineering-led organization operating from Paris and Tel Aviv offices.

Experience Level

Mid-level β€” typically requires 4+ years of experience in digital IC backend implementation.

Responsibilities

Primary responsibilities include:

  • Execute full-chip and block-level physical design tasks: floorplanning, placement, clock tree synthesis, routing, and physical verification.
  • Develop and optimize the digital backend flow and automation scripts.
  • Drive timing closure and power optimization efforts.
  • Perform physical verification activities (DRC/LVS/ERC) and address signoff criteria.
  • Collaborate with front-end designers to resolve timing and logical/physical interface issues.
  • Support tapeout preparation and final signoff processes.

Requirements

Must-have:

  • 4+ years of experience in digital IC backend implementation.
  • Proficiency with backend EDA tools, particularly Cadence Innovus and Genus.
  • Strong knowledge of place & route (P&R), static timing analysis (STA), DRC/LVS verification, IR drop, and electromigration (EM) analysis.
  • Experience with advanced technology nodes (22nm or below preferred).
  • Skilled in Tcl scripting for automation of backend flows.
  • Proficient English; French is a plus.

Nice-to-have:

  • Experience with hierarchical or full-chip implementation.

Education Requirements

Master's or PhD in Electrical/Electronic Engineering or a related field.


About the Company

Company: Arago

Arago is an AI and computer hardware startup (founded 2024) developing AI-driven semiconductor and photonics solutions. The company brings together engineers and researchers in photonics, electronics, software, mathematics, and machine learning to accelerate prototype-to-silicon development across hubs in France, North America, and Israel.

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Date Posted: 2026-08-27