DFT MBIST Staff Engineer

Job Title

DFT MBIST Staff Engineer

Role Summary

Senior hands-on contractor to implement, verify, and debug Memory BIST (MBIST) for complex SoC designs. The role focuses on Synopsys MBIST (SMS) insertion through pattern generation, simulation, and silicon bring-up. Remote position aligned to PST hours; 12+ month contract.

Experience Level

Senior - requires extensive hands-on DFT experience (typical expectation: 8+ years).

Responsibilities

Primary responsibilities are implementation, verification, and post-silicon support for MBIST on SoC designs.

• Perform MBIST insertion for complex SoC memories using Synopsys SMS.
• Integrate and verify MBIST at top level and resolve integration issues.
• Develop, run, and debug MBIST simulations (RTL, no-delay gate-level, and timing-aware with-delay simulations) using Synopsys VCS.
• Generate and validate MBIST test patterns using Vecgen and validate diagnostics.
• Debug RTL, simulation, and MBIST integration failures; perform root-cause analysis.
• Support silicon bring-up, characterization, and post-silicon debug related to memory failures and DFT infrastructure.
• Collaborate with DFT, RTL, Physical Design, and Product Engineering to resolve implementation issues.
• Independently drive issue resolution and document implementation flows and debug findings.

Requirements

Must-have technical experience and skills for immediate contribution; preferred items listed separately.

• 8+ years of hands-on DFT experience with significant focus on MBIST (must-have).
• Proven experience with Synopsys MBIST (SMS), preferably SMS5 and/or SMS6 (must-have).
• Proficiency with Synopsys VCS for MBIST verification and simulation (must-have).
• Experience with Vecgen for MBIST test pattern generation and validation (must-have).
• Deep understanding of MBIST flow: insertion, top-level integration, verification, pattern generation, diagnostics, simulation and debug (must-have).
• Knowledge of MBIST test algorithms (e.g., March) and memory repair schemes (BISR/BIRA, spare row/column allocation) (must-have).
• Experience with no-delay and with-delay (timing-aware) simulations and gate-level debug (must-have).
• Experience supporting silicon bring-up, post-silicon debug, and root-cause analysis of memory-related failures (must-have).
• Familiarity with Verilog/SystemVerilog and standard DFT methodologies (must-have).
• Scripting skills (Tcl, Perl, or Python) to automate MBIST flows and debug (preferred).
• Familiarity with ATPG and scan insertion flows and advanced SoC DFT integration (preferred).
• Ability to work independently with minimal supervision and strong communication skills (must-have).

Education Requirements

Not specified.

About the Company

Company: ICS Global Soft

Technology staffing and consulting firm providing contract and direct-hire IT and engineering professionals across semiconductor, software, and systems design — including DFT, verification, embedded, and other engineering roles.