ASIC Design Engineer

Job Title

ASIC Design Engineer

Role Summary

Design and verify digital ASICs for optical transceivers used in next-generation optical modems. Work within the engineering team on RTL development, verification, synthesis, timing closure and system integration.

Experience Level

Mid-level; typically requires 3+ years of experience in digital ASIC design and verification.

Responsibilities

Primary responsibilities include:

• Design and implement digital circuits using Verilog and SystemVerilog.
• Perform synthesis, timing analysis, linting, formal equivalence checks, and CDC analysis.
• Optimize designs for performance, power, and area (PPA).
• Develop and run RTL simulation and verification (including UVM/formal where applicable).
• Participate in design reviews and provide technical guidance to team members.
• Collaborate with cross-functional teams for system integration and validation.

Requirements

Must-have:

• 3+ years of experience in digital ASIC design and verification.
• Proficiency in Verilog and/or SystemVerilog.
• Strong understanding of digital design principles and ASIC design flow/tools.
• Experience with synthesis, timing closure, lint, formal verification, and CDC methodologies.
• Knowledge of low-power design techniques.
• Good problem-solving, communication, and teamwork skills.

Nice-to-have:

• Experience with DSP, digital communications, and FEC techniques.
• Scripting experience (Python, Tcl) for automation.
• Familiarity with optical communication standards and optical transceivers.

Education Requirements

Bachelor's degree or higher in Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: Celero Communications

Headquarters: Ottawa, Ontario, Canada

Designs and develops optical transceivers and ASIC solutions for next-generation optical modems, focusing on digital ASIC/RTL design, verification, and optical communication technologies.