ASIC Design Engineer – DSP / Analog / SerDes

Job Title

ASIC Design Engineer – DSP / Analog / SerDes

Role Summary

Design and implement digital ASIC blocks and contribute to mixed-signal ASICs for high-speed optical communication systems. Work inside a multi-discipline team to take blocks from architecture and RTL through implementation, tapeout, and silicon validation.

Experience Level

Mid-level — role expects approximately 5+ years of experience in digital ASIC design.

Responsibilities

Core responsibilities include design, implementation, integration, and verification of digital and mixed-signal ASIC functionality for high-speed optical systems.

• Design and implement digital circuits and ASIC blocks using Verilog/SystemVerilog.
• Develop and integrate DSP, digital communication, and high-speed SerDes functionality into ASIC designs.
• Collaborate with Analog, SerDes, DSP, Architecture, Verification, Physical Design, and Systems teams for mixed-signal integration.
• Develop high-speed datapaths, signal processing blocks, control logic, and interfaces for optical communication systems.
• Perform synthesis, static timing analysis, lint, formal equivalence, CDC, and other implementation/signoff activities.
• Optimize designs for performance, power, and area (PPA) and perform RTL simulation and debugging.
• Contribute to block- and top-level integration, verification, and silicon bring-up.
• Participate in architecture and design reviews and provide technical guidance.
• Develop automation and scripts (Python, Tcl, or similar) to improve design and verification efficiency.

Requirements

Must-have technical skills and experience.

• 5+ years of experience in digital ASIC design with ownership of complex blocks or subsystems.
• Strong proficiency in Verilog and/or SystemVerilog and RTL design methodologies.
• Hands-on experience with ASIC design flows and industry-standard EDA tools.
• Experience with synthesis, static timing analysis, Lint, CDC, formal verification, and RTL simulation.
• Strong knowledge in one or more of: Digital Signal Processing (DSP), high-speed SerDes, analog/mixed-signal ICs, digital or optical communications.
• Familiarity with verification methodologies such as UVM and/or formal verification.
• Experience collaborating with analog/mixed-signal teams and understanding analog/digital interfaces.
• Practical skills in PPA optimization, debugging, and cross-functional problem solving; good communication and teamwork skills.

Education Requirements

Bachelor's or higher degree in Electrical Engineering, Computer Engineering, or a related field.

Preferred Qualifications

Nice-to-have experience that strengthens candidacy.

• Experience designing ASICs for optical communications, optical transceivers, coherent communications, or high-speed networking.
• Experience with coherent DSP, FEC, modulation schemes, equalization, or high-speed data recovery.
• Experience with SerDes architectures (TX/RX, CDR, PLLs, CTLE, DFE), ADC/DAC interfaces, or related mixed-signal circuitry.
• Experience taking ASICs through synthesis, physical implementation, tapeout, and silicon bring-up.
• Experience with MATLAB, Python, Tcl, and working in startup or fast-paced semiconductor environments.

About the Company

Company: Celero Communications

Headquarters: Ottawa, Ontario, Canada

Designs and develops optical transceivers and ASIC solutions for next-generation optical modems, focusing on digital ASIC/RTL design, verification, and optical communication technologies.