Mentor ModelSim FPGA Design Engineer Jobs
FPGA simulation and verification roles built on ModelSim, common across defense, aerospace, industrial, and academic silicon teams.
Guides, industry insights, and career advice for IC engineers, ASIC designers, and chip architects.
FPGA simulation and verification roles built on ModelSim, common across defense, aerospace, industrial, and academic silicon teams.
Property-based verification roles built around JasperGold, from SVA assertions to closing formal proofs on connectivity, registers, and CDC.
Verification and implementation roles for engineers who own logical equivalence checking with Synopsys Formality across the ASIC flow.
Analog and mixed-signal roles for engineers who run Cadence Spectre and Virtuoso ADE as their primary circuit sign-off tool.
Physical verification roles built around Siemens Calibre, from DRC and LVS on foundry runsets to clean tapeout sign-off.
Physical design place-and-route roles built around Synopsys ICC2, from floorplan and CTS to timing-driven routing and PrimeTime signoff.
3D electromagnetic simulation roles built around Ansys HFSS, from package extraction to SERDES channel S-parameters.
Functional verification roles built around Siemens EDA Questa, from UVM regressions to Questa Formal and CDC closure.
Logic synthesis roles built around Synopsys Design Compiler, from DC Shell scripting to placement-aware DC-Topo.
Timing signoff roles built around Synopsys PrimeTime, from MCMM analysis to ECO-guided closure.
The simulator named in most DV postings, and what hiring teams expect you to run from compile to coverage.
The Cadence answer to Design Compiler, and what hiring teams expect you to drive from RTL to a clean netlist.