Siemens Calibre DRC LVS Engineer Jobs: Physical Verification
Every chip that reaches a foundry clears physical verification first, and at most companies that means Calibre. When a job description calls out Calibre DRC and LVS by name, it wants someone to own the last checks before tapeout, the point where a missed violation can cost a full mask set.
The core of the role is running Calibre DRC and LVS against foundry PDK runsets, reading the results, and driving them to zero. You interpret design rule violations layer by layer and chase LVS mismatches until the layout matches the schematic. Engineers who can also write or extend custom rule decks, instead of only running the foundry deck, tend to move up fast.
Calibre sits at the sign-off point for tapeout engineer jobs and for much of the daily grind in physical design engineer jobs, since the same clean-DRC bar gates both. Foundry PDKs from TSMC, Samsung Foundry, and GlobalFoundries ship Calibre runsets, which is a big reason the tool is so entrenched.
At advanced nodes the checks get heavier. Multi-patterning decomposition, EUV rules, and pattern matching push teams onto Calibre nmDRC, and verification stops being a rubber stamp at the end of the schedule. You also spend real time managing waivers and separating true violations from tool noise. Getting a runset to converge on a large block at 5nm or 3nm is engineering work, not a formality.
Because the skill is narrow and the cost of a mistake is a respin, physical verification pay holds up well. US base salaries for verification and tapeout-facing engineers commonly land in the rough range of $120K to $200K, with senior and staff total compensation higher at large fabless and foundry teams. The salary guide for semiconductor jobs has the level-by-level detail.
If you have taken a block from thousands of violations down to a clean sign-off, lead with that story: the node, the block size, and how you closed it. That beats a generic Calibre line on a resume. Save a search on semidesignjobs.com and new Calibre openings will land in your inbox.
FAQ
What are DRC and LVS in Calibre
DRC (Design Rule Check) confirms that layout geometry obeys the foundry's manufacturing rules, such as minimum widths, spacings, enclosures, and DFM rules on each layer. LVS (Layout versus Schematic) confirms that the physical layout matches the circuit netlist, catching opens, shorts, and wrong device placements that would fail in silicon. Calibre is the industry standard for both.
How do engineers debug LVS mismatches in Calibre
Calibre LVS reports mismatches as unmatched nets, devices, or ports between the extracted layout and the reference schematic. Engineers use the Calibre RVE (Results Viewing Environment) to walk the mismatch list, highlight each location in the layout editor, and trace the root cause, usually a missing via, a disconnected wire, or a wrong device type.
What is Calibre nmDRC
Calibre nmDRC is Siemens's physical verification platform for complex rules at advanced nodes, including multi-patterning decomposition, EUV-specific rules, pattern matching, and wafer-level statistical checks. Traditional Calibre DRC handles standard geometry rules, while nmDRC covers the computational lithography-aware rules that 7nm and below require.