Mentor Calibre DRC Physical Verification Jobs: Apply Now
Every chip that reaches a foundry passes through Calibre first. Mentor Calibre DRC physical verification jobs, now Siemens Calibre after the rebrand, cover the tapeout gate where a layout either clears the foundry's manufacturing rules or does not ship.
The core loop is running Calibre DRC against the foundry PDK rule deck, reading the violation categories that come back, and debugging them interactively in Calibre RVE. On advanced nodes a single PDK can carry hundreds of rule files and thousands of individual checks, so triage speed matters. Beyond DRC, most of these roles also touch LVS, ERC, and antenna checks on the path to a clean GDSII.
Senior candidates can read and edit SVRF, the rule-deck language, to add custom checks or handle design-specific exceptions rather than just running the deck the foundry hands over.
Physical design engineers often run Calibre Interactive from inside Cadence Virtuoso, highlighting a violation and jumping straight to the offending geometry in the layout editor instead of exporting GDSII for a separate batch run.
The work sits next to tapeout engineer jobs, and it overlaps heavily with Siemens Calibre DRC and LVS engineer jobs, which pair the same tool with netlist-versus-layout checking.
Openings show up at foundries, at fabless companies taking their own designs to GDSII, and at any team running leading-edge nodes where a missed density or antenna rule means a respin. Mobile SoC vendors, networking companies, and AI accelerator startups all keep Calibre engineers close to the tapeout schedule.
If physical verification is your track, browse physical design jobs and save a Calibre search on semidesignjobs.com to get an email when a tapeout-critical role opens.
FAQ
What DRC checks does Mentor Calibre perform
Calibre DRC covers minimum width and space rules on every metal layer, via enclosure rules, layer density and uniformity for CMP, pattern rules for advanced lithography, well and tap rules for ESD and latchup, and antenna rules that protect gate oxide. On advanced node PDKs that adds up to hundreds of rule files and thousands of checks.
How does the Calibre Interactive workflow help physical design engineers
Calibre Interactive runs inside Cadence Virtuoso or a similar layout environment and shows violations directly in the layout. You can highlight a violation, jump to its location in the editor, and fix the geometry on the spot, instead of exporting GDSII and running batch-mode Calibre separately.
What is the Calibre SVRF rule deck language
SVRF, the Standard Verification Rule Format, is the scripting language Calibre uses for DRC and LVS rule decks. Foundries ship SVRF decks in their PDK that encode every manufacturing rule. Experienced Calibre engineers read and modify SVRF to add custom checks, tune rule parameters, or write design-specific exceptions for particular cell types.